Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-02-16
2002-12-10
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06493850
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related in general to the field of electronic systems and semiconductor devices and more specifically to automated systems and methods for modeling integrated circuit characteristics for preventing destructive electrostatic discharge and latch-up.
DESCRIPTION OF THE RELATED ART
Integrated circuits (ICs) may be severely damaged by electrostatic discharge (ESD) events. A major source of ESD exposure to ICs is from the charged human body (“Human Body Model”, HBM); the discharge of the human body generates peak currents of several amperes to the IC for about 100 ns. A second source of ESD is from metallic objects (“Machine Model”, MM); it can generate transients with significantly higher rise times than the HBM ESD source. A third source is described by the “Charged Device Model” (CDM), in which the IC itself becomes charged and discharges to ground in the opposite direction than the HBM and MM ESD sources. More detail on ESD phenomena and approaches for protection in ICs can be found in A. Amerasekera and C. Duvvury, “ESD in Silicon Integrated Circuits” (John Wiley & Sons LTD. London 1995), and C. Duvvury, “ESD: Design for IC Chip Quality and Reliability” (Int. Symp. Quality in El. Designs, 2000, pp. 251-259; references of recent literature).
ESD phenomena in ICs are growing in importance as the demand for higher operating speed, smaller operating voltages, higher packing density and reduced cost drives a reduction of all device dimensions. This generally implies thinner dielectric layers, higher doping levels with more abrupt doping transitions, and higher electric fields—all factors that contribute to an increased sensitivity to damaging ESD events.
The most common protection schemes used in metal-oxide-semiconductor (MOS) ICs rely on the parasitic bipolar transistor associated with an NMOS device whose drain is connected to the pin to be protected and whose source is tied to ground. The protection level or failure threshold can be set by varying the NMOS device width from the drain to the source under the gate oxide of the NMOS device. Under stress conditions, the dominant current conduction path between the protected pin and ground involves the parasitic bipolar transistor of that NMOS device. This parasitic bipolar transistor operates in the snapback region under pin positive with respect to ground stress events.
The dominant failure mechanism, found in the NMOS protection device operating as a parasitic bipolar transistor in snapback conditions, is the onset of second breakdown. Second breakdown is a phenomenon that induces thermal runaway in the device wherever the reduction of the impact ionization current is offset by the thermal generation of carriers. Second breakdown is initiated in a device under stress as a result of self-heating. The peak NMOS device temperature, at which second breakdown is initiated, is known to increase with the stress current level.
Many circuits have been proposed and implemented for protecting ICs from ESD. One method that is used to improve ESD protection for ICs is biasing the substrate of ESD protection circuits on an IC. Other solutions offered in known technology require additional IC elements, silicon real estate, and/or process steps (especially photomask alignment steps). Their fabrication is, therefore, expensive. Examples of device structures and methods are described in U.S. Pat. No. 5,539,233, issued Jul. 23, 1996 (Amerasekera et al., “Controlled Low Collector Breakdown Voltage Vertical Transistor for ESD Protection Circuits”); U.S. Pat. No. 5,793,083, issued Aug. 11, 1998 (Amerasekera et al., “Method for Designing Shallow Junction, Salicided NMOS Transistors with Decreased Electrostatic Discharge Sensitivity”); U.S. Pat No. 5,940,258, issued Aug. 17, 1999 (Duvvury, “Semiconductor ESD Protection Circuit”); U.S. Pat. No. 6,137,144, issued Oct. 24, 2000, and U.S. Pat. No. 6,143,594, issued Nov. 7, 2000 (Tsao et al, “On-Chip ESD Protection in Dual Voltage CMOS); and U.S. patent application Ser. No. 09/456,036, filed Dec. 3, 1999 (Amerasekera et al., “Electrostatic Discharge Device and Method”).
In general, even good design and fabrication improvement steps are not able to completely eliminate ESD sensitivity of complex circuits. Consequently, predictive modeling at the circuit level has become extremely important since experimental methods require destructive testing, costly failure analysis to determine the effectiveness of a protection scheme, and often a frustrating redesign of the circuit. A first effort in this direction is described in U.S. Pat. No. 5,796,638, issued on Aug. 18, 1998 (Kang et al., “Methods, Apparatus and Computer Program Products for Synthesizing Integrated Circuits with Electrostatic Discharge Capability and Connecting Ground Rules therein”). A software system generates an IC schematic containing power rails and electrical paths interconnecting retrieved circuit elements and I/O pads. The resistances of the electrical paths to the I/O pads are then determined. Lengths and/or widths of the electrical paths and power rails are adjusted to eliminate/correct ground rules faults. The IC schematic is thus updated. The method is inadequate for extracting parasitic devices and considering substrate resistance effects.
Another design and verification effort is described in U.S. Pat. No. 6,086,627, issued on Jul. 11, 2000 (Bass et al., “Method of Automated ESD Protection Level Verification”). Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design and then verified; power rails are similarly checked. The method is inadequate for extracting parasitic devices and considering substrate resistance effects.
Modeling examples for designing and analyzing ESD protection circuits and detecting ESD design errors have been described in the papers “Modeling MOS Snapback and Parasitic Bipolar Action for Circuit-Level ESD and High Current Simulations” (by A. Amerasekera, S. Ramaswamy, M.-C. Chang, and C. Duvvury, Proc. Int. Reliab. Phys. Symp. 1996, pp. 318-326; extensive literature reference list), and “An Automated Tool for Detecting ESD Design Errors” (by S. Sinha, H. Swaminathen, G. Kadamati, and C. Duvvury, EOS/ESD Symp. 1998, pp. 208-217). In these papers, a system and flow are outlined to check a given IC design for ESD performance. The impact on detecting faulty IC component values and design errors is illustrated by a number of examples. However, contributions and impact of the substrate resistance network are not considered and options for optimizing the circuit parameters are not offered.
In the recent U.S. patent application Ser. No. 60/258,659, filed Dec. 29, 2000 (Ramaswamy et al., “Semiconductor Device Extractor for Electrostatic Discharge and Latch-up Applications”), a computerized system and method is disclosed for minimizing ESD and latch-up sensitivities in an IC design. This application combines input data from device layout, technology rules and doping profiles in order to extract netlists, element location and substrate resistance, analyze the layout for parasitic device formation. The application outputs lists of ESD- and latch-up sensitive elements and their locations. However, the application cannot simulate an actual ESD event in order to get a quantitative answer about value and location of ESD-sensitive elements. The present invention is related to this patent application.
An urgent need has, therefore, arisen for a coherent, low-cost system and method of quantitatively simulating an ESD event in an IC, while the IC is still in the design stage. The answers should be quantitative, and the system flexible enough for different semiconductor product families and a wide spectrum of design and process variations. Preferably, these innovations should also shorten IC design cycle time.
SUMMARY OF THE INVENTION
For quantitatively identifying sensitivities against electrostatic discharge (ESD) and latch-up in an integrated circuit (IC) design (before the actual IC is fabric
Duvvury Charvaka
Kadamati Gopalaro
Prasad Guru C.
Raghu C. S.
Ramaswamy Sridhar
Siek Vuthe
Tat Binh C.
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