Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-25
2003-04-01
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S246000, C438S386000
Reexamination Certificate
active
06541334
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the integrated technology field. More specifically, the present invention relates to an integrated circuit configuration which is arranged in a substrate and has at least one buried circuit element, and to an associated manufacturing method, and in particular to a DRAM memory with buried trench capacitors.
Integrated semiconductor memory circuits with such trench capacitors are, for example, memories with random access (RAM), dynamic memories (DRAM, dynamic random access memory), synchronous dynamic memories (SDRAM), and chips which combine logic functions and dynamic memories and are referred to as embedded DRAMs.
In order to illustrate the present invention, conventional trench capacitors such as are found, for example, in dynamic memories DRAMs will firstly be described.
FIG. 1
shows a conventional trench capacitor such as is used in particular in a DRAM semiconductor memory cell. Such a DRAM semiconductor memory cell is composed essentially of a capacitor
160
which is formed in a substrate
101
. The substrate is lightly doped with, for example, p-type dopants such as boron. A deep trench which is formed in the substrate is usually filled with polysilicon
161
which is heavily n+ doped with, for example, arsenic or phosphorus. A buried plate
165
which is doped with, for example, arsenic is located within the substrate
101
on a lower region of the trench. The arsenic or the dopant is usually diffused out into the silicon substrate
101
from a dopant source such as an arsenic silicate glass (ASG) which is formed on the side walls of the trench (temporarily for the doping process). The polysilicon
161
and the buried plate
165
serve here as electrodes of the capacitor
160
. A dielectric layer
164
separates the electrodes of the capacitor and serve as a capacitor dielectric.
In order to actuate the trench capacitor
160
, the DRAM semiconductor memory cell according to
FIG. 1
also has a selection transistor
110
. The transistor has a gate
112
and diffusion regions
113
and
114
. The diffusion regions which are spaced apart by a channel
117
are usually formed by implanting dopants, for example phosphorus. A contact diffusion region
125
connects the capacitor
160
to the selection transistor
110
in the process.
An insulating collar
168
is formed on an upper section or upper region of the trench. The insulating collar
168
prevents a leakage current to the diffusion region
125
in contact with the buried plate
165
. Such a leakage current is undesirable in particular in memory circuits because it reduces the charge holding time or retention time of a semiconductor memory cell.
According to
FIG. 1
, the conventional semiconductor memory cell with trench capacitor also has a buried well or layer
170
. The peak concentration of the dopants in the buried n-type well are located approximately at the lower end of the insulating collar
168
. The buried well or layer
170
serves essentially to connect the buried plates
165
of a multiplicity of adjacent DRAM semiconductor memory cells or capacitors
160
in the semiconductor substrate
101
.
Switching the selection transistor
110
by applying a suitable voltage to the gate
112
essentially permits access to the trench capacitor
160
, the word line usually simultaneously forming the gate at every second cell.
FIG. 1
thus shows an active word line
112
and a passive word line
120
. The diffusion region
113
is connected to a bit line
185
in the DRAM field. The bit line
185
is separated from the diffusion region
113
by a dielectric insulating layer
189
and is electrically connected to it via a contact
183
.
In addition, in order to insulate a respective semiconductor memory cell with associated trench capacitor from the adjacent cells, shallow trench isolation (STI)
180
is formed on the surface of the semiconductor substrate
101
. According to
FIG. 1
, what is referred to as the passing word line
120
(adjacent) can for example be formed above the trench, isolated by the shallow trench isolation
180
, providing what is referred to as a folded bit line architecture.
In this way, a conventional semiconductor memory cell which is suitable for highly integrated circuits is obtained. A disadvantage with such semiconductor memory cells is, however, the use of the insulating collar
168
, in particular in the case of greater integration or further shrinking. In order to avoid parasitic vertical field effect transistors and to raise a switch-on voltage above the operating voltage, this insulating collar
168
will in future generations also have to have a minimum thickness which is dependent on the respective operating voltage. For this reason, it is difficult to scale this conventional trench capacitor to, for example, structure sizes of less than 100 nm when the circuit elements are arranged according to the prior art. To be more precise, the upper region of the trench becomes a problem area and leads to an increased series resistance, and in extreme cases to choking off of the internal electrode of the capacitor.
In order to avoid this problem, the art has provided a further semiconductor memory cell with trench capacitor. The conventional memory cell, which is illustrated in
FIG. 2
, is formed, for example, in an SOI substrate (silicon on insulator). Such a conventional trench capacitor is known, for example, from U.S. Pat. No. 5,770,484 (see EP 0 848 418 A2). Identical reference symbols designate here identical layers or elements to those in
FIG. 1
, and a detailed description is dispensed with for reasons of simplicity.
The essential difference from the trench capacitor illustrated in
FIG. 1
is essentially the substrate used, which comprises what is referred to as an SOI substrate. Here, according to
FIG. 2
there is an insulating layer
190
on a carrier substrate
101
, and a semiconductor substrate
200
over the insulating layer
190
. Owing to the use of such a substrate, the selection transistor
110
is completely electrically isolated from the trench capacitor
160
, preventing any parasitic vertical transistors from being formed. The use of a collar can be completely dispensed with here, as a result of which a greater integration capacity or further shrinking is possible. A disadvantage with such a conventional SOI trench capacitor is, however, the extraordinarily high manufacturing costs which result in particular from the provision of the expensive SOI substrate. It would also be desirable to be able to form the buried insulating layer only locally in order to permit simpler integration into the current process.
SUMMARY OF THE INVENTION
The object of the present invention is to provide an integrated circuit configuration with at least one buried circuit element and a manufacturing method which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and which can be implemented even for structures of less than 100 nm in a simple and cost-effective fashion.
With the above and other objects in view there is provided, in accordance with the invention, an integrated circuit configuration, comprising:
a substrate having a surface;
at least one circuit element formed in the substrate near the surface;
at least one buried circuit element formed in the substrate and spaced apart from the circuit element near the surface; and
an insulating layer locally delimited in the substrate and disposed between the circuit element near the surface and the buried circuit element.
With the above and other objects in view there is also provided, in accordance with the invention, a method of manufacturing an integrated circuit configuration with at least one buried circuit element. The method comprises the steps of:
forming a multiplicity of trenches in a substrate;
forming an outer conductive layer on lower regions of the trenches within the substrate, defining first capacitor plates;
forming dielectric layers in the trenches, defining capacitor dielect
Luetzen Jörn
Sell Bernhard
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Pham Hoai
Pham Long
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