Integrated circuit chip wiring structure with crossover...

Details Integrated circuit chip wiring structure with crossover... Integrated circuit chip wiring structure with crossover...

1996-11-22

2003-06-10

Paladini, Albert W. (Department: 2125)

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

C174S262000, C174S264000, C361S767000, C361S771000

Reexamination Certificate

active

06576848

ABSTRACT:

TECHNICAL FIELD
This invention generally relates to the manufacturing of integrated circuit chip wiring structures, especially dynamic random access memory (DRAM) chips, and more specifically relates to a method of producing these chips without the use of vias between some layers, while still providing cross-over and contact capabilities.
BACKGROUND OF THE INVENTION
Integrated circuit (IC) chips, for example dynamic random access memory (DRAM) and static random access memory (SRAM), require different resistance and capacitance limits in the cell array wiring and the sense amplifier/decode and support circuits. In the array wiring, the conductor is customized for low capacitance. For example, in a typical 4 Megabit(M) DRAM the capacitance (C) is less than or equal to (≦) 0.15 femptofarads per micron (ff/&mgr;m) in bitline-to-bitline wiring at the expense of resistance (R), which is less than or equal to 1 ohm per square (&OHgr;/□). On the other hand, in the supports and decode circuits (the logic circuits), the resistance is optimized (R≦0.07 &OHgr;/□), while capacitance is less crucial (C≦0.25 ff/&mgr;m).
In order to achieve these resistance and capacitance limits, the pitch, which is defined as the width of the line plus the space between the lines, of the wiring structure must be carefully controlled. In order for the wiring to be suitable for the array requirements (capacitance and resistance), the pitch must be as near as possible to the smallest photolithographically achievable size (minimum pitch). Although some minimum pitch wiring is needed in the supports, for the most part the logic circuitry has a pitch about two times the minimum pitch in order to carry the signals with the requisite lower resistance. Various ways of creating the necessary line widths have been suggested. See Cronin, J. and C. Kaanta, “Thickness Controlled Thick and Thin Lines in One Damascene Level”,
IBM Technical Disclosure Bulletin
(TDB) No. 7, at 393-94 (Dec. 1990); Cronin, John, “Method to Make Thin and Thick Lines Within a Single Level of Damascene Wiring Using a Single Photomask”,
IBM TDB
No. 7 at 387 (Dec. 1990); Cronin et al., “Optimum Metal Line Structures for Memory Array and Support Circuits”,
IBM TDB
Vol. 30, No. 12, at 170-71 (May 1988); Cronin et al., Method for Obtaining Low Resistance and Low Capacitance Metalization (Sic) Using Single Metal Deposition,
IBM TDB
Vol. 30, No. 12, at 142-43 (May 1988); and Anonymous, Process to Make Thick and Narrow Conductive Lines,
IBM Research Disclosure
, No. 313 (May 1990)
As shown in
FIG. 1
, the necessary line widths were initially constructed by depositing and defining a first metal layer Ml that was thin, covering the first metal layer M
1
by depositing a layer of an insulating material I, followed by depositing and defining a second metal layer M
2
that was thick. Contacts between the first and second metal layers M
1
, M
2
were formed by etching a tapered via V through the insulator I and then depositing the second metal layer M
2
over the insulator I. Thus, contact was made between the first and second layer M
1
, M
2
through the tapered via V.
It was then found that a planarized layer of insulative material was desirable for improved photolithographic resist image definition (the planar surface minimized depth of field problems).
FIG. 2
illustrates the solution wherein a first metal layer (thin) M
1
was deposited and defined. The insulator I was next deposited over the entire surface and planarized. Studs S were formed by etching a vertical via V through the insulator layer I, depositing a stud via metal M
3
therein, and planarizing the surface. The second metal layer (thick) M
2
was then applied and patterned so that connection between first and second metal M
1
, M
2
was made through the stud via S.
As shown in
FIG. 3
, further improvements to minimize cost by eliminating processing steps and materials were made by combining the stud via metal with the second metal layer M
2
. In this method, the first metal layer (thin) M
1
was defined and deposited followed by an insulator layer I which was deposited and planarized. The second metal layer's M
2
wiring lines in the insulator I were defined as trenches T and stud vias S were defined as holes H. Metal was deposited to fill the trenches T and holes H and the metal was then planarized. (see also FIG.
13
). By defining the trenches T first and then the studs S, before metallizing, the one metal deposition filled both the trenches T and holes H thereby saving costs. This approach to wiring is known as the “damascene approach”.
The “damascene” approach to wiring is well known in the industry. It comprises depositing an insulator over the semiconductor device structures, e.g. M
1
. Next, the insulator is planarized by a chemical-mechanical polish (CMP) process. A resist material is applied, exposed to an energy source, and developed, leaving openings in certain regions. These openings define wiring channel regions/trenches. The insulator exposed in the resist openings is subjected to a reactive ion etch (RIE) to remove the exposed areas of insulator. The remaining resist material is then removed, leaving the planar insulator with channels or trenches cut into it. A conformal metal is applied over the entire surface, filling all the trenches and covering all the insulator surfaces. The metal is removed by a planarization, e.g., a CMP, process. The metal is only left in the trenches, forming wiring channels.
Adding a via level requires extra layers which must be sequentially defined. Each additional step to the process requires another alignment step, which increases the likelihood of failure of the final product. Additionally, each processing step requires further handling of the chips which increases cycle time. By reducing the number of steps and layers, there is a reduction in handling and delays, which also tends to increase the yield of the chips because there are fewer defects introduced through handling. In addition, yield is enhanced by the elimination of process variables related to the uncontrolled delays which are created when the chips are processed with several extra steps in the production line. The processing characteristics of the materials used in the production of the chips can vary depending on extent of time elapsed from one processing step to the next. By reducing the number of steps, these delays are reduced and more repeatable, thus reducing process variability. These increases in yield result in cost savings to the manufacturer. Additionally, the removal of the intervening insulator results in cost savings both because of the reduced material costs and because of the reduced handling costs.
In the manufacture of dynamic random access memory (“DRAM”) chips, containing the costs of production is essential. One way of reducing cost is to eliminate as many process steps as possible. One possibility is to eliminate a separate, trapped via level between the first metal and the second metal, if possible. Typically the first metal is a thin layer while the second metal is thick. Since the thin metal is required only in the DRAM array for low capacitance and the thick metal is required in the supports for low resistance, one could limit the design rules so that a cross-over between the thin and thick lines is not required and therefore a via connection between the thick and thin layers is not required. However, it should be noted that a via level between two wiring levels allows the two levels to cross each other, and connect when a via is defined at the cross-over, but not connect if there is no via at the cross-over.
FIGS. 4 and 5
show two variations of an approach called the “multi-damascene” approach, that create thick and thin wiring levels without both a separate, trapped via level and cross-over capability. The method, as shown in the
FIGS. 4 and 5
, creates thin lines M
1
by the damascene method in a thin insulator I
thin
, followed immediately by a second, thick line M
2
in a thick insulator I
thick
by the damasc

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