Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-12-05
2006-12-05
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C257S700000, C257S758000
Reexamination Certificate
active
07146596
ABSTRACT:
An integrated circuit chip having a contact layer that includes a plurality of Vdd, Vddx, ground and I/O contacts arranged in a generally radial pattern having diagonal and major axis symmetry and generally defining four quadrants. A multilayer X-Y power grid is located beneath the contact layer. A wiring layer is interposed between the contact layer and power grid to provide a well-behaved electrical transition between the generally radial Vdd, Vddx and ground contacts and the rectangular X-Y power grid. The interposed wiring layer includes concentric square rings of Vdd, Vddx and ground wires located alternatingly with one another. The Vddx wires are discontinuous between adjacent quadrants so that the magnitude of Vddx may be different in each quadrant of the chip if desired.
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Increased Chip Wireability Through More Efficient Power Distribution, IBM Technical Disclosure Bulletin, vol. 38, No. 09, pp. 243-245, Sep. 1995.
Bednar Thomas R.
Budell Timothy W.
Buffet Patrick H.
Caron Alain
Crain, Jr. James V.
Downs Rachlin & Martin PLLC
International Business Machines - Corporation
Rossoshek Helen
Thompson A. M.
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