Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond
Reexamination Certificate
2002-08-06
2004-07-20
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Die bond
C257S784000, C257S690000, C257S691000, C257S692000, C257S786000
Reexamination Certificate
active
06765301
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit bonding device and a manufacturing method thereof, particularly to an integrated circuit bonding device with highly integrated signal trace lines immune from noise and a manufacturing method thereof.
2. Description of the Related Art
In an integrated circuit manufacturing process, gold lines are bonded between pads on a chip and fingers on a substrate before molding. Thus, the solder balls or pins, connection points hereinafter, of the substrate for connection and signal transmission with external circuits are electrically connected to the pads of the chip.
FIG. 1
is a diagram showing a conventional integrated circuit with bonded gold lines arranged. The integrated circuit comprises a substrate
10
, a chip
12
and gold lines
14
A,
14
B, and
14
C. The chip
12
has pads
16
A,
16
B, and
16
C to output signals comprising strobe signals, clock signals, power signals, and ground. The signals are connected to the connecting points
17
A,
17
B, and
17
C of the substrate
10
through gold lines
14
A,
14
B, and
14
C, then connected to other circuits by lines
18
A and
18
B through via
19
A, and
19
B or only by line
18
C.
The ground ring
15
A and power ring
15
B surround the chip
12
. The power circuit composed by the ground ring
15
A and power ring
15
B provides the necessary power for chip
12
to operate.
However, noise is easily generated in each signal trace line carrying high frequency signals such as the clock, strobe, and data signals since they interfere with each other. Interfered signals cause failure in chip
12
. Therefore, the bonding and layout of the circuit have to be modified to decrease the interference between the signals to improve the reliability of the circuit.
SUMMARY OF THE INVENTION
The object of the present invention is to provide an integrated circuit bonding device and a manufacturing method thereof. The signal trace lines transmitting important signals are shielded by the metal lines transmitting the power or ground signals from the pad of the chip to the substrate and follow-up circuits. Because the signal in the power line or ground line is stable and has a stronger electric current, the electromagnetic waves generated from the adjacent signal trace lines are attracted to the power line or ground line. Therefore, the important signals are not interfered with by the adjacent signal trace lines. Using the power line or ground line to shielding metal lines with important signals to solve the interference between the signals and combining the design of the position of pads, the quality of signals is improved.
To achieve the above-mentioned object, the present invention provides an integrated circuit bonding device. The substrate includes a signal connection point and two shielding connection points set at the two sides of the signal connection point. The chip is set on the substrate. There are a signal pad and two shielding pads set at the two sides of the signal pad on the edge of the chip. The signal gold line is coupled to the signal connection point and the signal pad. Two shielding gold lines are coupled to the shielding connection points and the shielding pads and extend along both sides of the signal gold line. The signal trace line is set on the substrate and coupled to the signal connection point. The power circuit is set on the substrate and coupled to the shielding connection points. The power circuit includes two shielding lines extending along both sides of the signal trace line.
In addition, the present invention provides a method to manufacture an integrated circuit device. First, a substrate and a chip are provided. Next, a signal pad is formed on the chip. Two shielding pads are formed at both sides of the signal pad on the edge of the chip. Two shielding connection points are formed on the substrate responding to the shielding pads. Then, a signal connection point is formed between the shielding connection points. Next, a signal trace line is formed for coupled to the signal connection point. A signal gold line is formed for coupled to the signal pad and the signal connection point. Next, two shielding gold lines are formed for coupled to the shielding pads and the shielding connection point and extending along both sides of the signal gold line. Finally, a power circuit comprising two shielding lines extending along both sides of the signal trace line is formed on the substrate.
REFERENCES:
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patent: 5801440 (1998-09-01), Chu et al.
patent: 6054767 (2000-04-01), Chia et al.
patent: 6291898 (2001-09-01), Yeh et al.
patent: 6476472 (2002-11-01), Davison et al.
patent: 6477046 (2002-11-01), Stearns et al.
patent: 6489682 (2002-12-01), Yet et al.
patent: 6534879 (2003-03-01), Terui
patent: 6570249 (2003-05-01), Liao et al.
Liang Kuei-Chen
Lin Wei-Feng
Wu Chung-Ju
Loke Steven
Silicon Integrated Systems Corp.
Vu Quang
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