Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2010-05-20
2011-10-25
Zarneke, David (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257SE23179
Reexamination Certificate
active
08044526
ABSTRACT:
A method of packaging an integrated circuit die including forming a mask window having a first aperture with a first set of alignment edges and forming an alignment feature on an uppermost surface of the integrated circuit die where the alignment feature has a second set of alignment edges. The alignment feature is inserted into the first aperture. The integrated circuit die is mechanically biased until the first and second set of alignment edges are in physical contact with one another and the alignment feature is secured into the mask window, thus forming an integrated circuit die assembly.
REFERENCES:
patent: 5216806 (1993-06-01), Lam
patent: 6048744 (2000-04-01), Corisis et al.
patent: 6300018 (2001-10-01), Dilley et al.
patent: 6455933 (2002-09-01), Akram et al.
patent: 7087992 (2006-08-01), Chua et al.
patent: 2001/0012643 (2001-08-01), Asada
patent: 2001/0033014 (2001-10-01), Koh
patent: 2002/0037598 (2002-03-01), Koh
patent: 2002/0168797 (2002-11-01), DiStefano et al.
patent: 2003/0042603 (2003-03-01), Koh
patent: 2005/0032070 (2005-02-01), Raimundo et al.
patent: 2006/0032070 (2006-02-01), Biggs et al.
patent: 2008/0160670 (2008-07-01), Lam
patent: WO-2008/083028 (2008-07-01), None
“U.S. Appl. No. 11/616,479, Final Office Action mailed Jan. 22, 2010”, 6 pgs.
“U.S. Appl. No. 11/616,479, Interview Summary and Final Office Action mailed Feb. 22, 2010”, 8 pgs.
“U.S. Appl. No. 11/616,479, Non-Final Office Action mailed May 14, 2009”, 9 pgs.
“U.S. Appl. No. 11/616,479, Response filed Oct. 29, 2009 to Restriction Requirement mailed Sep. 29, 2009”, 10 pgs.
“U.S. Appl. No. 11/616,479, Response filed Aug. 14, 2009 to Non-Final Office Action mailed May 14, 2009”, 9 pgs.
“U.S. Appl. No. 11/616,479, Restriction Requirement mailed Sep. 29, 2009”, 4 pgs.
International Patent Application No. PCT/US07/88321, Search Report mailed Apr. 24, 2008, 2 pgs.
“International Patent Application No. PCT/US07/88321, Written Opinion mailed Apr. 24, 2008”, 6 pgs.
Atmel Corporation
Fish & Richardson P.C.
Zarneke David
LandOfFree
Integrated circuit assemblies with alignment features and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit assemblies with alignment features and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit assemblies with alignment features and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4286178