Integrated circuit arrangement and design method

Details Integrated circuit arrangement and design method Integrated circuit arrangement and design method

2011-05-17

2011-05-17

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000

Reexamination Certificate

active

07945828

ABSTRACT:
An integrated circuit (IC) arrangement (10) comprises an integrated circuit (100) having a digital circuit portion (120) with a plurality of digital outputs (122), each of the outputs being arranged to provide a test result in a test mode of the integrated circuit (100). The arrangement (10) further comprises space compaction logic (140) comprising a space compaction network (160) having a plurality of compaction domains (162), each domain being arranged to compact a plurality of test results into a further test result, and a spreading network (150) coupled between the plurality of digital outputs (122, 210) and the space compaction network (160), the spreading network being arranged to duplicate each test result from the digital outputs (122,210) to a number of compaction domains (162). This space compaction logic (140), which may be located on the IC100or external thereto such as on a test apparatus or on a test interface, reduces the risk of fault cancellation or fault aliasing compared to SCLs without spreading network.

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Krishnendu, Chakrabarty; et al “Zero-Aliasing Space Compaction of Test Responses Using Multiple Parity Signatures” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6, No. 2, Jun. 1998, pp. 309-313.
Sinanoglu, O; et al “Parity-Based Output Compaction for Core-Based SOCs” European Test Workshop, 2003. Proceedings. The 8th IEEE. May 25, 2003, pp. 15-20.
Das, Sunil; et al “Fault Tolerance in Systems Design in VLSI Using Data Compression Under Constraints of Failure Probabilities” IEEE Transactions on Instrumentation and Measurement, vol. 50, No. 6, Dec. 2001.

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