Integrated circuit and testing method for integrated circuit

Details Integrated circuit and testing method for integrated circuit Integrated circuit and testing method for integrated circuit

2005-12-20

2005-12-20

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C324S765010

Reexamination Certificate

active

06978409

ABSTRACT:
In testing of a plurality of logic circuits having the same function and included in an integrated circuit, an address decoder makes two logic circuits having the same function simultaneously operate in response to an address signal. Try state buffers enter an enable state in response to a testing mode signal. Accordingly, the outputs of the two logic circuits are output to a signal line through the try state buffers. When the two logic circuits are both nondefective, a supply current cannot be measured by a current measuring unit, but when one of the logic circuits is defective, an excessive supply current is measured by the current measuring unit, and hence, it can be determined that one of them is defective. Accordingly, a plurality of logic circuits can be simultaneously found defective or nondefective by the IDDQ testing, resulting in reducing time required for the testing.

REFERENCES:
patent: 5459737 (1995-10-01), Andrews
patent: 6134688 (2000-10-01), Sachdev

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