Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-12-22
2004-02-10
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S741000
Reexamination Certificate
active
06691270
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an integrated circuit and method of operation of such a circuit, and in particular to integrated circuits that use serial test scan chains for applying signals to and capturing signals from predetermined circuit elements within an integrated circuit.
2. Description of the Prior Art
Integrated circuit testing using serial test scan chains is known from the JTAG system that is the subject of IEEE Standard 1149.1-1990. In accordance with this Standard, an entire integrated circuit is treated as a whole and tested together.
However, as the complexity of integrated circuits has increased, it has become more desirable to test individual circuit elements within the integrated circuit, and accordingly integrated circuits have been developed which incorporate a number of separate serial test scan chains, each being coupled to a different circuit element to be tested.
Typically, testing hardware external to the integrated circuit will access the test scan chain via a scan chain controller provided on the integrated circuit, the scan chain controller having a serial interface for communicating with the testing hardware.
Where multiple serial test scan chains are provided, it is known to provide a scan chain selecting instruction which is decoded by the scan chain controller to cause the scan chain controller to capture a scan chain specifying value received at the serial interface, and to use that scan chain specifying value to select a serial test scan chain upon which further instructions received at said serial interface are to be effected. A description of such a scan chain selecting instruction is provided in U.S. Pat. No. 5,636,227.
Hence, to specify an instruction to be applied in relation to a desired scan chain, it is first necessary to scan a scan chain selecting instruction into the scan chain controller, then to scan the appropriate scan chain specifying value into the scan chain controller, and then to scan in the actual instruction to be applied. It has been found that this process can impact on the efficiency of the testing procedure, particularly in scenarios where this process is repeated many times.
Accordingly, it would be desirable to improve the efficiency of the testing procedure when the above process is required.
SUMMARY OF THE INVENTION
Viewed from a first aspect, the present invention provides an integrated circuit comprising: a plurality of circuit elements; a plurality of serial test scan chains each coupled to a different one of said circuit elements; a scan chain selector responsive to a specified scan chain specifying value to select a corresponding one of said plurality of test scan chains; a scan chain controller having a serial interface for receiving signals from outside of said integrated circuit, said scan chain controller comprising an instruction decoder for decoding scan chain controller instructions received from said serial interface; the decoder being responsive to a first scan chain controller instruction to specify a predetermined scan chain specifying value and a second scan chain controller instruction for decoding by the decoder.
It has been found that there are a number of testing procedures where much of the testing involves using only a subset of the scan chain controller instructions in relation to a subset of the available test scan chains. Given this fact, the present invention specifies a first scan chain controller instruction that is arranged to cause the decoder to specify a predetermined scan chain specifying value and a second scan chain controller instruction. Accordingly, in situations where the predetermined scan chain specifying value corresponds to a frequently used scan chain, and the second scan chain controller instruction is a frequently used instruction in relation to that scan chain, then the use of the first scan chain controller instruction can significantly improve the efficiency of the testing procedure by avoiding the requirement for the multi-step process described earlier each time that instruction is to be applied in relation to that scan chain.
In preferred embodiments, the integrated circuit further comprises: an instruction register for storing a scan chain controller instruction to be decoded by the decoder; and a scan chain register for storing a scan chain specifying value to be referenced by the scan chain selector to determine which test scan chain to select. Typically, both the instruction register and the scan chain register will reside within the scan chain controller, as will the scan chain selector in preferred embodiments.
In one embodiment, the decoder may be arranged to be responsive to the first scan chain controller instruction to cause the predetermined scan chain specifying value to be written into the scan chain register, and the second scan chain controller instruction to be written into the instruction register.
However, it has been found that a more efficient approach is to cause the decoder to simulate appropriate outputs from the instruction register and the scan chain register without actually storing either the predetermined scan chain specifying value or the second scan chain controller instruction in the scan chain register and instruction register, respectively. More particularly, in preferred embodiments, the decoder is responsive to the first scan chain controller instruction to simulate as the output of the instruction register the second scan chain controller instruction and to simulate as the output of the scan chain register the predetermined scan chain specifying value without the contents of the instruction register and scan chain register being updated.
In preferred embodiments, the integrated circuit further comprises a first multiplexer located between the instruction register and the decoder having a first input connected to the instruction register and a second input arranged to receive the second scan chain controller instruction, the decoder incorporating a pre-decoder responsive to the first scan chain controller instruction to cause the first multiplexer to output the instruction received at the second input. It will be appreciated that the first multiplexer and pre-decoder can be incorporated as part of the decoder itself. However, by embodying the first multiplexer and the pre-decoder function as a separate logical function to the remainder of the decoder, this avoids the requirement to make any alterations to the instruction decoder itself.
Further, in preferred embodiments, the integrated circuit further comprises a second multiplexer located between the scan chain register and the scan chain selector having a first input connected to the scan chain register and a second input arranged to receive the predetermined scan chain specifying value, the pre-decoder being responsive to the first scan chain controller instruction to cause the second multiplexer to output the data received at the second input.
It will be appreciated that the above described techniques could be employed in relation to the testing of a variety of different circuit elements that have scan chains associated therewith. However, in preferred embodiments, one of the circuit elements is an instruction transfer register for specifying an instruction to be executed by a microprocessor of the integrated circuit, and the predetermined scan chain specifying value identifies a test scan chain incorporating a shift register for shifting data into said instruction transfer register. In these preferred embodiments, the testing procedure is actually used not to test the integrated circuit as such, but to debug applications executing on the integrated circuit. In particular the testing mechanism of the invention is used to access on-chip hardware such as the instruction transfer register to enable application debugging.
In such preferred embodiments, the decoder is preferably responsive to the second scan chain controller instruction to cause the scan chain selector to be coupled to the serial interface to enable instruction
Allue Conrado Blasco
Devereux Ian Victor
ARM Limited
Lamarre Guy J.
Nixon & Vanderhye P.C.
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