Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2009-06-10
2011-12-20
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230030
Reexamination Certificate
active
08081528
ABSTRACT:
An integrated circuit includes a memory; a memory test circuit that tests the memory; and an input/output port, wherein the memory test circuit includes a latch circuit that outputs output of the memory, an address of the memory to be accessed is changed in accordance with a first clock signal, and output of the memory corresponding to the changed address is latched in accordance with a latch signal having a cycle of an integral multiple of the first clock signal, data of the latch circuit is output via the input/output port in a cycle of the latch signal, an address of a memory cell corresponding to the output of the memory to be latched by the latch circuit is changed, and the latch and the output is repeated.
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Arent & Fox LLP
Fujitsu Semiconductor Limited
Ho Hoai V
Lappas Jason
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