Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-06-27
2004-12-21
Graybill, David E. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S773000, C257S775000, C257S786000
Reexamination Certificate
active
06833557
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and packaging and, more particularly, to providing mechanisms and methods to assess an integrated circuit.
BACKGROUND OF THE INVENTION
Integrated circuits are typically fabricated with multiple levels of patterned metallization electrically separated by interlayer dielectrics that contain vias at selected locations to provide electrical connections between the patterned metallization layers. As integrated circuits are scaled to smaller dimensions in a continual effort to provide increased performance (e.g., by increasing device speed and providing greater circuit functionality within a given area chip), the interconnect line width dimension becomes increasingly narrow and the number of metal levels increases. This renders them more susceptible to deleterious effects such as fracture induced by delamination of mold compound and stress migration. Stress migration refers to mass transport of the interconnect material in response to mechanical stress gradients present in the interconnects which result from thermal expansion coefficient mismatches and compliance mismatches between the conductive runners and surrounding (e.g., overlying and/or underlying) dielectric materials or mold compounds.
Depending on the thermal history, the stress may be either compressive or tensile. Tensile stress can cause void formation, whereas compressive stress can cause hillock formation. Voids continue to grow to reduce the stress until it is energetically unfavorable for them to continue to grow, and migrating voids may also coalesce with other voids thus providing an effective void growth mechanism. For instance, consider the process of depositing an interlayer dielectric over an aluminum (Al) line (often termed “runner”) which rests on a substrate or other dielectric material overlying a semiconductor substrate. Typically, such deposition is performed by chemical vapor deposition (CVD). After deposition, as the structure cools toward room temperature, the aluminum line, having a thermal expansion coefficient much greater than the interlayer dielectric, wishes to contract more than the overlying interlayer dielectric.
The interlayer dielectric, which has very good adhesion to the aluminum layer, prevents the aluminum line from contracting to its desired equilibrium length, thus resulting in a tensile stress in the aluminum line. The tensile stress is greatest at the edges of the line and decreases toward the center; hence there is a non-zero tensile stress gradient across the width of the line. This stress gradient corresponds to a chemical potential gradient that represents a thermodynamic driving force for mass transport. Accordingly, aluminum atoms diffuse to reduce the overall strain energy in the aluminum line. Over time, typically many months or several years, this mass transport of the conductive layer generates voids in the conductive runners that can lead to failure. The voids may entirely traverse the line (i.e., open circuit), or may reduce the cross-sectional area through which current may be conducted such that electrornigration effects are exacerbated and/or current conduction causes a catastrophic thermal failure event.
Essential to assessing the stress migration properties of conductive runners, is a method for evaluating these effects. Particularly, such methods should ri provide a mechanism that provides easy assessment of potential stress problems.
SUMMARY OF THE INVENTION
The present invention is directed to an apparatus and process to assess the occurrence or the likelihood of a failure in an integrated circuit. The process includes forming a conductive region such as a runner about the periphery of a substrate or die. The conductive region may be located at one or more different metallization layers within the integrated circuit. The conductive region is coupled to one or more of the bonds pads. The die is assessed by measuring the resistance, conductivity, cross talk or other electrical characteristics on the conductive region via the bond pads. The assessment can then be used to predict whether, for example, the runners formed in the integrated circuit have failed or are likely to fail.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
REFERENCES:
patent: 5563445 (1996-10-01), Iijima et al.
patent: 5726491 (1998-03-01), Tajima et al.
patent: 5811874 (1998-09-01), Lee
patent: 6201308 (2001-03-01), Ikegami et al.
Ryan Vivian Wanda
Shilling Thomas Herbert
Agere Systems Inc.
Graybill David E.
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