Integrated circuit and a method of making an integrated...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S637000, C438S672000, C257S368000, C257S385000

Reexamination Certificate

active

07745275

ABSTRACT:
A method of forming an integrated circuit68provides over a diffusion region28on a substrate26a gate electrode36. A source electrode is provided by a source local interconnect conductor30and a drain electrode is provided by a drain local interconnect conductor32. An insulator layer38is formed over these electrodes and respective electrode openings are formed through the insulator layer38so as to provide electrical connection to a Metal1 layer46, 48, 50. The etching process for the electrode openings is controlled such that the maximum etching depth is insufficient to penetrate through the insulating layer38and accordingly short circuit a gate insulator layer34provided between the diffusion region28and the gate electrode36. Thus, the gate opening may be positioned over the diffusion region28. Double patterning followed by separate etching steps for the gate opening and the source/drain opening may be used to control the gate opening depth and permit the gate contact to be position overlying the diffusion region.

REFERENCES:
patent: 5804846 (1998-09-01), Fuller
patent: 6072221 (2000-06-01), Hieda
patent: 6869850 (2005-03-01), Blosse et al.
patent: 6946376 (2005-09-01), Chediak et al.
patent: 7547594 (2009-06-01), Yang
patent: 2003/0003640 (2003-01-01), Lee
patent: 2004/0245581 (2004-12-01), Tsuchiaki
patent: 2005/0236694 (2005-10-01), Wu et al.

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