Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-12-15
2004-06-22
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C365S201000
Reexamination Certificate
active
06754865
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit with a semiconductor memory and a logic circuit. More particularly, the present invention relates to an improvement enabling efficient tests of the semiconductor memory even if a bus width of an internal data bus between the semiconductor memory and the logic circuit is wider than that of an external data bus between the logic circuit and data input/output terminals.
2. Description of Related Art
FIG. 14
is a block diagram showing a conventional integrated circuit. In the figure, the reference numeral
53
designates an integrated circuit formed on a semiconductor substrate;
54
designates a semiconductor memory formed as a part of the integrated circuit
53
;
55
designates a logic circuit formed on the same semiconductor substrate as the semiconductor memory
54
;
56
designates internal signal lines connected between the semiconductor memory
54
and the logic circuit
55
;
57
designates an external input/output terminal; and
58
designates external signal lines connected between the logic circuit
55
and a plurality of external input/output terminals.
Next, the operation of the conventional integrated circuit will be described.
When certain signals are sent from the external input/output terminals
57
, each signal is transmitted to the logic circuit
55
through the external signal lines
58
. Based on this input and the like, if necessary, the logic circuit
55
then accesses the semiconductor memory
54
through the internal signal lines
56
.
Since the conventional integrated circuit
53
is thus constructed, signals in the external input/output terminals
57
cannot be directly input to/output from the semiconductor memory
54
. Accordingly, in order to perform tests on the semiconductor memory
54
by using the test technique for a single memory (a memory without a logic circuit
55
) as described in Patent Kokai HEI9(1997)-231794 and Patent Kokai HEI11(1999)-16393, an input/output selector should be provided for direct connection between the external input/output terminals
57
and the semiconductor memory
54
.
However, even if the above technique is used, the bit number of data which can be written to and read out of the semiconductor memory
54
at a time is limited to as few as the number of the external input/output terminals
57
for inputting/outputting data to/from the logic circuit
55
. There is thus a problem in that, in such an integrated circuit
53
containing both a logic circuit
55
and a semiconductor memory
54
(hereinafter referred to as “logic-memory-combined integrated circuit”), although the memory capacity has increased due to recent advances in high integration technique, tests of the memory cannot be performed with the efficiency of a single memory with a great number of external data input/output terminals
57
.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the above problem involved in such a logic-memory-combined integrated circuit. An object of the present invention is to provide an integrated circuit wherein a semiconductor memory can be efficiently tested corresponding to the degree of its large capacity while suppressing or preventing an increase in number of input/output terminals for use in the test.
According to the present invention, there is provided An integrated circuit comprising; a semiconductor memory for receiving m-bit internal data (m is an integer of 2 or more) in and outputting the data from an internal address; a logic circuit for receiving the m-bit internal data from and outputting the data to the semiconductor memory while designating the internal address; an internal data bus connected between the semiconductor memory and the logic circuit, having m internal data lines, for transmitting the m-bit internal data between the semiconductor memory and the logic circuit; a data input/output terminal group for receiving n-bit external data (n is less than m and an integer of 1 or more) from and outputting the data to outside; an external data bus connected between the logic circuit and the data input/output terminal group, having n external data lines, for transmitting the n-bit external data between the logic circuit and the external data input/output terminal group; at least one simultaneous write circuit, each connected to a plurality of internal data lines and an external data line, for receiving bit data which is at least a part of n-bit data in the external data bus from the external data line, dividing the data into a plurality of bit data of a same value, and outputting the divided data to the internal data lines, thereby the m-bit data being produced from the n-bit data in the external data bus and output to the internal data bus; and at least one coincidence judgement circuit, each connected to same internal data lines and external data line as those which a corresponding simultaneous write circuit is connected to, for effecting coincidence judgement of data in these internal data lines and outputting a coincidence judgement result to the external data line, the number of the coincidence judgement circuit(s) being equal to that of the simultaneous write circuit(s).
Here, a bit number “m” of the internal data may be “L” times a bit number “n” of the external data wherein L is an integer of 2 or more; the simultaneous write circuits and the coincidence judgement circuits may be provided one for every L internal data lines; and each of the coincidence judgement circuits may change a level of an output to be provided to an external data line depending on coincidence/incoincidence.
The semiconductor memory may comprise: a plurality of memory blocks each comprising: a plurality of memory cells arranged in a matrix layout; a plurality of word lines extending along one direction of the layout of the memory cells; a plurality of bit lines extending along another direction of the layout of the memory cells; a sense amplifier connected to an internal data line; and a plurality of selectors each connecting a bit line to the sense amplifier: a line address decoder for applying a selection voltage to one of the word lines: and a row address decoder for applying a selection voltage to one of the selectors.
The integrated circuit may further comprise a switching decoder between the memory blocks and the line address decoder or the row address decoder, connected to word lines or bit lines more than lines which the line address decoder or the row address decoder is connected to, for intercepting a selection voltage for a certain word line or bit line supplied from the line address decoder or the row address decoder and supplying it to a line of the excess word lines or bit lines.
Switching decoders may be provided one for every internal data lines connected to a simultaneous write circuit and a coincidence judgement circuit between the memory blocks and the row address decoder.
Switching decoders may be provided one for every L/j internal data lines (j is an integer of 2 or more) between the row address decoder and the memory blocks: and the integrated circuit further comprises partial judgement means; the means having j partial coincidence judgement circuits, connected one to every L/j of internal data lines connected to a coincidence judgement circuit, for effecting coincidence judgement for the connected L/j internal data lines; the partial judgement means for outputting different signals depending on which partial coincidence judgement circuit judges incoincidence.
The partial judgement means may have a display circuit for receiving outputs from the two partial coincidence judgement circuits and outputting signals of different levels depending on which circuit judges incoincidence.
The partial judgement means may have a serial circuit for switching a plurality of outputs from the partial coincidence judgement circuits in sequence to serially output them to the outside.
The partial judgement means may have an encoder for receiving a plurality of outputs from the partial coincidence ju
Burns Doane Swecker & Mathis L.L.P.
De'cady Albert
Gandhi Dipakkumar
Renesas Technologyy Corp.
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