Integrated circuit

Details Integrated circuit Integrated circuit

1998-03-12

2000-06-06

Tu, Trinh L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

060732601

ABSTRACT:
Test data TD, which are provided to a flipflop 11 of a scan flipflop 10-1 through a scan path 1S are latched with the timing of a clock signal CK that has been inverted at an inverter 12. An output signal S11 from the flipflop 11 is provided to a flipflop 14 via a selector 13, is latched at the flipflop 14 with the timing of the clock signal CK and is provided to a scan flipflop 10-2at the succeeding stage through a scan path 3S. In this manner, since the timing with which the test data TD change and the timing with which the clock signal CK rises are offset by 1/2 of the clock cycle, a reliable scanning operation is achieved regardless of the length of the paths such as the scan path 1S and the like.

REFERENCES:
patent: 5394404 (1995-02-01), Uchida
patent: 5459735 (1995-10-01), Narimatsu
patent: 5487074 (1996-01-01), Sullivan

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