Integrated bipolar junction transistor for mixed signal...

Details Integrated bipolar junction transistor for mixed signal... Integrated bipolar junction transistor for mixed signal...

2000-07-18

2001-10-16

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S234000, C438S309000

Reexamination Certificate

active

06303420

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to the field of integrated circuit bipolar junction transistors and more specifically to a novel method to achieve high performance bipolar junction transistors integrated with high performance CMOS transistors with reduced masked steps.
BACKGROUND OF THE INVENTION
For mixed signal circuits it is often important to have high performance bipolar junction transistors integrated with high performance CMOS transistors on the same chip. The bipolar junction transistors will be used for analog signal processing for such functions as providing silicon bandgap reference voltages. Current mixed signal integrated circuits contain bipolar junction transistors fabricated using dedicated processes that require extra masking steps and specific implant conditions tailored for the bipolar junction transistor. These extra masking steps and specific implants conditions add extra cost to fabricating these mixed signal integrated circuits.
High performance CMOS transistors for mixed signal applications require a number of different implants to form the n-type and p-type wells. They also require NMOS and PMOS threshold voltage adjust implants, NMOS and PMOS drain extension implants, NMOS and PMOS pocket or halo implants, and NMOS and PMOS source-drain implants. The n-type and p-type well implants form the regions in the semiconductor body where the PMOS and NMOS transistors will be formed. The NMOS and PMOS threshold voltage adjust implants set the threshold voltages for these transistors by varying the substrate doping beneath the transistor gate dielectric. The very short transistor gate length used in mixed signal CMOS transistors make them susceptible to hot carrier injection. To reduce this effect, NMOS and PMOS drain extension implants (LDD) are utilized. In this disclosure, LDD will be used to represent any drain extension type implant. The drain extension typically extend the heavily doped source and drain regions further under the gate of the transistor. In high performance mixed signal CMOS transistors, pocket or halo implants are used to reduce the effect of the short transistor gate length on transistor properties such as threshold voltage. The effect of the pocket implant is not however limited to threshold voltage. The pocket implant for a particular transistor type usually results in a doping profile that extends beyond the drain extension of the transistor.
A number of mixed signal integrated circuits require a bipolar junction transistor with a beta(&bgr;) greater than 5. There is therefore great need for a reduced masking step process that will result in high performance integrated circuit bipolar junction transistor integrated in a circuit with high performance CMOS transistors.
SUMMARY OF THE INVENTION
The instant invention is a method to achieve high performance bipolar junction transistors integrated with high performance CMOS transistors using a reduced number of masking steps. The method comprises: providing a semiconductor body; forming a collector region of said integrated circuit bipolar junction transistor with a plurality of implants; forming a base region of said integrated circuit bipolar junction transistor with a metal oxide semiconductor transistor pocket implant; and forming a emitter region of said integrated circuit bipolar junction transistor with a metal oxide semiconductor transistor drain extension implant.
The main advantage of the method is the integration of a high performance bipolar junction transistor with MOS transistors without adding additional photolithographic masking steps.


REFERENCES:
patent: 5888861 (1999-03-01), Chien et al.
patent: 6001701 (1999-12-01), Carroll et al.
patent: 6117716 (2000-09-01), Manning
patent: 595484-A1 (1994-05-01), None
patent: 613181-A2 (1994-08-01), None
patent: 736898-A2 (1996-01-01), None
patent: 789400-A2 (1997-08-01), None

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