Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2001-03-08
2003-05-27
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S784000, C438S787000, C438S760000, C438S763000
Reexamination Certificate
active
06569782
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an insulating layer, a semiconductor device and methods for fabricating the same, and more particularly, to an insulating layer, a semiconductor device and methods for fabricating the same that includes a borophosphosilicateglass (BPSG) layer to control the additive amounts of boron (B) and phosphorous (P) most efficiently.
2. Description of the Related Art
Semiconductor devices require high capacity and fast operating speeds to power today's electronic devices. Accordingly, semiconductor device manufacturing methods continually strive to improve the integration density, reliability, and response times of the devices. As one example, consider the DRAM memory class, where 16M and 64M devices are being mass produced, 256M devices are starting to be mass produced, and plans for mass production of 1G devices are being explored.
Critical techniques to improve the integration density of semiconductor devices include layer fabricating techniques for insulating and conductive layers. The layer fabricating techniques can largely be classified into physical vapor deposition and chemical vapor deposition. The chemical vapor deposition technique provides a gas source, which includes supplying an element of an object material to be formed, and a reaction gas onto a substrate, and then forms a layer on the substrate by heating the substrate to initiate a chemical reaction.
As the semiconductor devices become more advanced, the parameters and requirements for the processing techniques to form a layer used for fabricating a semiconductor device are becoming more rigorous. This is because the insulating layers and conducting layers are formed in a multi-layer structure, and those layers have to be formed in a fine pattern with a design rule of 0.15 &mgr;m or less.
When those layers are formed to have the fine patterns, the process characteristics for making the fine pattern affect not only the layer on which the fine pattern is formed, but also the underlying and upper layers. Therefore, when the layers are formed, the chemical and physical characteristics of the other layers must be considered when deciding on the process characteristics of the layer to be formed.
A phosphosilicateglass (PSG) layer, which dopes phosphorus into an oxidized material, or a BPSG layer, which dopes boron and phosphorus into an oxidized material, are the primary layer types used for an insulating layer to protect a surface or to electrically isolate a metal wire. This is mainly due to the excellent step coverage of the PSG layer or the BPSG layer. Also, the PSG or BPSG layers getter alkali ion while reacting as a diffusion wall against humidity, and the processes for forming the layers can easily be performed in a low temperature regime.
However, there is a disadvantage to using PSG or BPSG layers. Since these layers have enough fluidity and create a diffusion wall during a reflow process, the layers also operate as an intermediary to pass on the humidity to the underlying layers. Accordingly, in a case where a layer is composed of a material that can be damaged by humidity, or an underlying substrate is made of silicon, it may cause a serious problem. Therefore, a method to minimize the influence of the humidity has to be fully considered when the PSG and BPSG layers are being formed.
Examples for forming PSG and BPSG insulating layers are disclosed in U.S. Pat. No. 4,668,973 (issued to Dawson et al.), Japanese Patent Laid-Open No. Sho 59-22945, Japanese Patent Laid-Open No. Hei 1-122139, and Japanese patent Laid-Open No. Hei 8-17926.
In U.S. Pat. No. 4,668,973, the PSG layer is formed by adding 7% or less of phosphorus into a nitride silicon layer after forming the nitride silicon layer on the substrate. Accordingly, the nitride silicon layer prevents the humidity from penetrating into the substrate even though the PSG layer has been reflowed. Furthermore, even if a window is formed at the PSG layer, since the substrate is not directly exposed by means of the nitride silicon layer, the substrate may be prevented from being oxidized.
In Japanese Patent Laid-Open No. Sho 59-222945, a nitride silicon layer is formed on a substrate and then a BPSG layer is formed on the nitride silicon layer. The nitride silicon layer prevents the humidity from penetrating into the substrate even though the BPSG layer has been reflowed. Therefore, it is able to prevent the substrate from being oxidizing by direct exposure.
In Japanese Patent Laid-Open No. Hei 1-122139, a nitride silicon layer is successively formed on the substrate and a gate electrode and thereafter a BPSG layer containing boron is formed. Therefore, the nitride silicon layer prevents the humidity from penetrating into the substrate or the gate electrode even though the BPSG layer has been reflowed.
In Japanese Patent Laid-Open No. Hei 8-17926, an oxide silicon layer is formed onto a polysilicon layer and then the BPSG layer is formed onto the oxide silicon layer. Therefore, the oxide silicon layer prevents the humidity from penetrating into the polysilicon layer or the substrate even if the BPSG layer has been reflowed.
In this way, when forming the insulating layer including the PSG layer or BPSG layer, the effect of the humidity can be minimized by means of forming the PSG layer or BPSG layer on the underlying nitride silicon layer. Also, the nitride silicon layer prevents the underlying layer or the substrate from being damaged by means of etching, for example, when a portion of the insulating layer is patterned and etched to form a window.
In the present fabricating method for a semiconductor device having elevated regions and recessed regions composed of minute windows or gate electrodes, one must consider the need to sufficiently force or charge the BPSG insulating layer into the recessed regions of the windows or the gate electrodes. Therefore, a chemical vapor deposition using a tetraethylorthosilicate (TEOS), a triethylborate (TEB), a triethylphosphate (TEPO), an oxygen gas and an ozone gas is employed to form the BPSG layer.
The BPSG layer is formed as follows. First, an oxidizing atmosphere for easily forming the BPSG layer is prepared using oxygen gas. After forming a first seed layer onto an etch stop layer comprising the nitride silicon layer using the TEOS and the oxygen gas, a second seed layer is formed onto the first seed layer using the triethylborate (TEB), the triethylphosphate (TEPO), the tetraethylorthosilicate (TEOS) and the oxygen gas. The constituents of the first and second seed layers determine the amount of boron and phosphorous added into the BPSG layer. Subsequently, the BPSG layer is formed onto the etch stop layer including the first and the second seed layers by using the triethylborate, the triethylphosphate, the tetraethylorthosilicate and the ozone gas. With this method, the BPSG layer is formed with a relatively large amount of phosphorous because the triethylphosphate is used to form the second seed layer.
While the BPSG layer has sufficient fluidity for normal circumstances, in a subsequent reflow process with nitrogen gas, the BPSG layer is not fully charged or filled into the recessed regions voids are frequently generated.
Therefore, oxygen gas and hydrogen gas are sometimes used instead of nitrogen gas to reflow the BPSG layer to minimize the generation of voids. However, when the BPSG layer has been reflowed with the oxygen gas and the hydrogen gas, the thickness of the etch stop layer under the BPSG layer is decreased. This is because phosphoric acid H
3
PO
4
is generated by a chemical reaction between the triethylphosphate, which determines the amount of phosphorus, and the oxygen gas and the hydrogen gas, which acid etches the etch stop layer while reflowing progresses.
Indeed, the thickness of the etch stop layer decreased by about 30% after reflowing with oxygen/hydrogen according to an analyzed result of the etch stop layer before and after the reflow with a transmission electron microscope (TEM). Also, using auger electro
Choi Byoung-Deog
Jeon Jin-Ho
Seo Tae-Wook
Yi Jong-Seung
Díaz José R.
Lee Eddie
Samsung Electronics Co,. Ltd.
Volentine & Francos, PLLC
LandOfFree
Insulating layer, semiconductor device and methods for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Insulating layer, semiconductor device and methods for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Insulating layer, semiconductor device and methods for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3060518