Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-05-26
2002-04-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S758000
Reexamination Certificate
active
06372628
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of laminated wiring layers, or multilayer wiring layers separated by insulating layers, and such an insulating film, as well as a manufacturing process for such a semiconductor device.
2. Description of the Related Art
As integration becomes more and more dense for a semiconductor large-scale integrated circuit (LSI), individual devices with dimensional accuracy of ¼ &mgr;m or less are now integrated near the surface of a Si substrate. An LSI exhibits its function only after its individual devices are connected by wiring. However, if wiring is detoured to avoid intersections in interconnections between the individual devices, interconnecting delay may be caused because area occupied by wiring or wiring length is increased. A technique has been commonly used for providing wiring on multiple layers by inserting insulating layers between wiring to prevent intersections and/or overlapping of wiring.
This concept of multilayer wiring is shown in FIG.
16
. An insulating film
1631
is formed in a silicon substrate
161
, and is formed with a contact hole
164
therein. A contact plug
164
is buried in the contact hole
164
to connect a device forming region
162
to a first wiring layer
1651
. In addition, the first wiring layer
1651
is connected to a second wiring layer
1652
through a via plug
1661
filled in a via hole
1661
opened in the insulating film
1632
. The second wiring layer
1652
is connected to a third wiring layer
1653
through a via plug
1662
filled in a via hole
1662
opened in the insulating film
1633
. Further multilayer wiring can be attained by sequentially repeating the process described above. The process is completed by covering the last wiring layer with a sealing film
167
.
This technique for multilayer wiring with thin insulating layers therebetween has a large stray capacity causing interconnecting delay. When a signal containing high frequency components is transmitted through two vertically adjacent wiring layers having an inter-layer insulating film therebetween, crosstalk is generated, thereby causing erroneous operation. To prevent interconnecting delay or crosstalk, it is sufficient to increase the distance between the upper and lower wiring, or to thicken the inter-layer insulating film. However, thickening the inter-layer insulating film makes it necessary to form a deep, contact hole or via hole. Formation of a deep contact hole or via hole makes it further difficult to perform the dry etching technology for forming these holes. Thus, it is desirable to have the thinnest inter-layer insulating film as possible. The semiconductor integrated circuit technology for 256 megabit DRAM (Dynamic Random Access Memory) or thereafter requires a smaller contact hole diameter of ¼ &mgr;m or less. However, if it is desired to hold a ratio of the depth of a contact hole to its diameter, or an aspect ratio, up to five from the viewpoint of the dry etching technology, the thickness of the inter-layer insulating film is necessarily required to be 1 &mgr;m or less. While the problem on the stray capacity between the upper and lower wiring layers is addressed in the above, an increase of stray capacity is also serious between wiring formed on a same plane. It is because, as the semiconductor integrated circuit is miniaturized, thickness of wiring and distance between wiring are also miniaturized, necessarily leading to the same problem as in the wiring thickness of ¼ &mgr;m. Since the wiring spacing cannot be widened in view of the requirement for a high degree of integration, the problem on interconnecting delay or crosstalk is more serious between wiring disposed on the same layer than between the upper and lower wiring for which the inter-layer insulating film may potentially be thickened.
To accurately determine interconnecting delay and crosstalk accompanying an increase of inter-wiring capacity determined by the thickness of the upper and lower inter-layer insulating film or the inter-layer insulating film in the same plane, it is necessary to handle it as a distributed constant circuit. FIG,
14
shows the capacity per unit wiring length between a wiring layer insulated by a silicon oxide film with a thickness H (dielectric constant: 3.9) and wiring on a silicon substrate, which is described by L. M. Dang, et al. in “IEEE Electron Device Letters,” Vol. EDL-2, 1981, p. 196. It shows that, as wiring width W decreases, capacity C significantly increases by a so-called fringe effect when compared with the so-called plane parallel plate approximated capacity. It is also known that the higher wiring height T is, the larger capacity C is. Although the insulating film between the silicon substrate and the lowermost wiring as shown in
FIG. 14
is not usually called an inter-layer insulating film, it is common in the problems of interconnecting delay and crosstalk. Thus, the inter-layer insulating film referred to in this specification includes an insulating film contacting the silicon substrate and performing electric insulation with the wiring as well. In addition,
FIG. 15
described in the above-referenced paper shows that, as wiring spacing is miniaturized, the total capacity Cf with the silicon substrate per unit length increases as further miniaturization is attained and when W/H is more than 1. This results because, although the capacity C
11
between the wiring and the silicon substrate decreases, the capacity C
12
between adjacent wiring separated by wiring spacing S contrarily increases. That is, although operating speed can be increased for individual elements of a semiconductor integrated circuit through miniaturization, wiring resistance and stray capacity increases in the wiring interconnecting these elements by miniaturization. Consequently, the operating speed for the entire LSI is not improved at all. Both of
FIGS. 14 and 15
show results of analysis on the stray capacity between the silicon substrate and the wiring disposed through an insulating film, however, they do not address the stray capacity between the wiring layers, even though the situation is the same for the stray capacity between the wiring layers.
Thus, it is an urgent necessity, in light of the foregoing discussion, to develop an inter-layer insulating film with a low dielectric constant &egr;r in place of Si
3
N
4
(&egr;r: 7 or less) and silicon oxide (&egr;r: 3.9 or less) which are insulating films commonly used in the LSI technology. An amorphous carbon fluoride film with a dielectric constant &egr;r<3 is disclosed in Japanese Patent Application Laid-Open Nos. 08-83842, 08-222557, 08-236517 and the like is expected as a suitable material with a low dielectric constant &egr;r.
BRIEF SUMMARY OF THE INVENTION
As described above, since the amorphous carbon fluoride film has a low dielectric constant &egr;r, it is expected to be suitable as an inter-layer insulating film in multilayer wiring. However, there are still problems in the technology of forming a contact hole contacting a semiconductor diffusion layer or a via hole for connecting wiring layers, which prevent it from being put in practical use. The inventors tried to open a hole in an amorphous carbon fluoride by referring to the description in Japanese Patent Application Laid-Open No. 5-74962 which is directed to an inter-layer insulating film which is believed to be a film similar to the amorphous carbon fluoride disclosed in Japanese Patent Application Laid-Open Nos. 08-83842, 08-222557, 08-236517. Japanese Patent Application Laid-Open No. 5-74962 shows that conventional photolithography technology can be used, thus the process is to use conventional resist which is a mixture of phenol resin and photosensitive agent or a resin such as cyclized rubber and photosensitive resin, to apply it on an amorphous carbon fluoride film in a thickness of 1-1.5 &mgr;m, and to open a hole with a diameter of 0.2 &mgr;m by assuming a highly integrated LSI of 64 megabit
Endo Kazuhiko
Horiuchi Tadahiko
Ishigami Takashi
Ito Shinya
Matsubara Yoshihisa
NEC Corporation
Nhu David
Sughrue & Mion, PLLC
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