Insulated gate field-effect transistor with gate-drain overlap a

Details Insulated gate field-effect transistor with gate-drain overlap a Insulated gate field-effect transistor with gate-drain overlap a

1991-03-27

1992-11-10

Wojciechowicz, Edward J.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

437 41, 437233, 257344, 257900, H01L 2906, H01L 21265

Patent

active

051628848

ABSTRACT:
A method of forming an insulated-gate field-effect transistor, and the transistor formed thereby, is described. According to a first embodiment, an inverted-T gate structure is formed by the deposition of a polycrystalline silicon layer, followed by the deposition of a metal silicide layer thereover. The metal silicide layer is etched with etchant which does not significantly etch polysilicon, to define the upper portion of the gate electrode. The reachthrough lightly-doped source/drain extensions are then implanted through the polysilicon layer, using the upper gate electrode portion as a mask. Sidewall spacers are formed on the sides of the upper portion of the gate electrode, and the polysilicon etched using the spacers as a mask, to define the inverted-T gate structure. In addition, either with the inverted-T gate structure or in conjunction with conventional gate structures, a method is disclosed which uses a first sidewall film to define the location of the source/drain implant relative to the LDD regions, and a second sidewall spacer to space direct react silicide formation from the gate, so that the dimensions of the graded junction may be defined independently from that of the silicidation reaction.

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