Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-02-16
2003-02-04
Whitehead, Jr., Carl (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S349000, C257S508000
Reexamination Certificate
active
06515332
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to insulated-gate field-effect semiconductor devices, particularly but not exclusively of the so-called “SOI” (semiconductor on insulator) type, and further relates to methods of manufacturing such semiconductor devices.
Insulated-gate field-effect semiconductor devices are known, having source and drain regions in a semiconductor body portion at a first major surface of a semiconductor substrate, and a gate electrode on a gate-dielectric layer between the source and drain regions for controlling a conduction channel in a channel region between the source and drain regions in an on-state of the device. A gate-terminal metallisation is connected to the gate electrode for applying a potential to the gate electrode. Source-terminal and drain-terminal metallisations are connected respectively to the source and drain regions.
United States patent specification U.S. Pat. No. 4,408,384 (our ref: PHB32654) discloses such a known device in which the gate-terminal and drain-terminal metallisations are present at the upper major surface of the body portion, whereas the source-terminal metallisation is present at an opposite major surface of the semiconductor substrate. A source connection is present between the source region and the semiconductor substrate to connect the source region to the source-terminal metallisation via the semiconductor substrate. U.S. Pat. No. 4,408,384 discloses a method of manufacturing this device in which the source connection is carried by a trench in the form of a V-shaped groove etched across the thickness of the semiconductor body portion to the substrate. The whole contents of U.S. Pat. No. 4,408,384 are hereby incorporated herein as reference material.
The provision of the source-terminal metallisation at the opposite major surface of the semiconductor substrate is advantageous in making better use of the layout area for the gate-terminal and drain-terminal metallisations and their connections at the upper major surface of the body portion. By mounting the substrate on a conductive lead-frame (or other conductor of the device package), a simple connection can be made to the source-terminal metallisation at the opposite major surface of the semiconductor substrate. However this arrangement of the source-terminal metallisation increases the on-resistance of the device, by adding the resistance due to the thickness of the substrate. If the substrate is thinned so as to reduce the electrical resistance therethrough to the source-terminal metallisation, then handling the device becomes less easy.
SUMMARY OF THE INVENTION
According to the present invention there is provided an insulated-gate field-effect semiconductor device, in which source and drain regions are present at a semiconductor body portion at a first major surface of a semiconductor substrate, and the gate-terminal metallisation is present at an opposite second major surface of the semiconductor substrate. A gate connection is present between the gate electrode and the semiconductor substrate to connect the gate electrode to the gate-terminal metallisation via the semiconductor substrate.
The gate-terminal metallisation serves for applying a potential to the gate electrode. Thus, in a device in accordance with the present invention, the part of the gate connection provided by the substrate does not increase the on-resistance of the main current path through the device, i.e. between the source and drain. Thus, the arrangement of the gate-terminal metallisation at the opposite major surface of the semiconductor substrate is advantageous in permitting better use of the layout area for source-terminal and drain-terminal metallisations (and their connections) at the upper major surface of the body portion, without introducing an on-resistance penalty. By mounting the substrate on a conductive lead-frame (or other conductor of the device package), a simple connection can be made to the gate-terminal metallisation at this opposite major surface of the semiconductor substrate.
The present invention can be particularly advantageous for a SOI device configuration, in which the semiconductor body portion is present on an insulating layer at the first major surface of the semiconductor substrate. The insulating layer may be sufficiently thin and of suitable dielectric that the gate-connected substrate itself acts as a second insulated gate adjacent to the body portion. This gate effect of the substrate can enhance the effect of the actual gate electrode in controlling turn-on of the device. In a particularly advantageous form, the gate connection can be carried by a trench in the body portion. The trench can extend through the insulating layer in order to carry the gate connection to the substrate.
The gate connection between the gate electrode and the substrate may be formed by extending the gate electrode itself and/or by providing an additional layer or region. Thus, this connection may comprise a metal layer and/or a semiconductor region. The region may be, for example a doped semiconductor region of the body portion and/or of the substrate. The metal layer may contact a semiconductor area of the substrate and/or of the body portion. It may extend on, for example, an insulating layer. The insulating layer may be present on the semiconductor body portion (for example on its upper surface and/or on a side wall) and/or on the gate electrode. The gate connection may be buried under the gate electrode (for example in a trench in the semiconductor body portion). The gate electrode may extend on a gate-dielectric layer on the upper surface of the body portion. In another form, the gate electrode may be a trench-gate in the semiconductor body portion. In this latter case, the gate connection may be a buried connection that is carried by a second trench, from the trench-gate across a remaining thickness of the semiconductor body portion to the substrate.
A particularly advantageous aspect of the present invention is in facilitating the integration of a p-n junction protection diode in parallel with the insulated gate of the device. The diode may be formed from pre-existing regions of the device (by changing the layout) and/or by providing additional regions or additional dopings. Thus, in a device in accordance with the invention, the semiconductor body portion may also comprise a p-n junction diode between the channel region of a first conductivity type and a diode region of the opposite second conductivity type. The diode region of the second conductivity type may be a region of increased doping concentration in the substrate and/or body portion. This diode region may form part of the gate connection in the body portion or substrate, and/or it may be contacted by the gate connection, for example at the side wall of a trench carrying the gate connection in the body portion. Thus, the diode region of the second conductivity type can be readily connected to the gate electrode by the gate connection. Indeed, the diode may be provided by a mask layout redesign, without requiring any additional process steps. A series of the diodes may even be formed.
REFERENCES:
patent: 4408384 (1983-10-01), Lowis et al.
patent: 4763183 (1988-08-01), Ng et al.
patent: 5382818 (1995-01-01), Pein
patent: 5808346 (1998-09-01), Ueda
patent: 6072215 (2000-06-01), Kawaji
patent: 6133610 (2000-10-01), Bolam
patent: 6172402 (2001-01-01), Gardner
patent: 6191455 (2001-02-01), Shida
Biren Steven R.
Jr. Carl Whitehead
Koninklijke Philips Electronics , N.V.
Rose Kiesha
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