Instruction processing pattern generator controlling an integrat

Details Instruction processing pattern generator controlling an integrat Instruction processing pattern generator controlling an integrat

1998-11-13

2000-11-28

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

712242, G01R 3128, G06F 1100

Patent

active

061548650

ABSTRACT:
A pattern generator for an integrated circuit tester includes an instruction memory storing addressable instructions (INST) and reading out each instruction when addressed by an address (ADDR) supplied as input thereto. An instruction processor receives each instruction read out of the instruction memory and alters the address input to the instruction memory in accordance with the received instruction so that the instruction memory reads out a next instruction. The instruction processor, which includes a conventional return address stack, is capable of executing conventional address increment, call and return instructions. The instruction processor is also capable of executing a temporary return instruction (TEMP) by incrementing its current address output to produce a new return address, by setting its address output to the value of a return address previously saved in the stack, by popping the saved return address from the stack, and by pushing the new return address onto the stack. Temporary return instructions enable instruction program flow to pass back and forth between a main program and a called subroutine.

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patent: 4493045 (1985-01-01), Hughes, Jr.
patent: 5321701 (1994-06-01), Raymond et al.
patent: 5337045 (1994-08-01), Shirasaka

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