Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-09-30
2001-02-06
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
68, 68
Reexamination Certificate
active
06184135
ABSTRACT:
BACKGROUND OF THE INVENTION
1) Field of the Invention
This invention relates generally a semiconductor device and a method for manufacturing and more particularly to a structure of a MOS transistor having a metal silicide film formed on a source and a drain region and a method for manufacturing the MOS transistor and more particularly to a method for forming a metal silicide contact to a substrate and more specifically to a multilayered device metallization suitable for use in small geometry semiconductor devices and to methods for its fabrication.
2) Description of the Prior Art
There is a trend in the semiconductor industry toward fabricating larger and more complex functions on a given semiconductor chip. The larger and more complex functions are achieved by reducing device sizes and spacing and by reducing the junction depth of regions formed in the semiconductor substrate. Among the feature sizes which are reduced in size are the width and spacing of interconnecting metal lines and the contact openings through which the metalization makes electrical contact to device regions As the feature sizes are reduced, new problems arise which must be solved in order to economically and reliably produce the semiconductor devices.
As both the contact size and junction depth are reduced, a new device metallization process is required to overcome the problems which are encountered. Historically, device interconnections have been made with aluminum or aluminum alloy metallization. Aluminum, however, presents problems with junction spiking which result from dissolution of silicon in the aluminum metallization and aluminum in the silicon. This problem is exacerbated with the small device sizes because the shallow junction is easily shorted and because the amount of silicon available to satisfy the solubility requirements of the aluminum metallization is only accessed through the small contact area, increasing the resultant depth of the spike. Adding silicon to the aluminum metallization has helped to solve this problem, but has, in turn, resulted in silicon precipitation and other problems.
A variety of solutions have been attempted to overcome the problems inherent with aluminum metallization. For example, the device region exposed through a contact opening has been metallized with chemical vapor deposited (CVD) tungsten. The tungsten is deposited by the reduction of WF6 with hydrogen. The WF6, however, initially reacts with the silicon surface, employing silicon from the contact area in the region. This results in what has become known in the literature as “worm holes” or tunnels in the silicon which can also cause shorting of the underlying junction. The use of sputtered instead of CVD tungsten would overcome the problem of reaction with the silicon, but sputtered tungsten is unable to reduce any native oxide film which may be present on the surface of the device region. The remaining oxide film results in high contact resistance. A further attempt at solving this problem has employed the use of a reactive silicide to make the initial contact to the device region. The silicide is then contacted with aluminum. The suicide makes a low resistance contact to the silicon, but the silicide-aluminum contact has the same problem as does the use of aluminum directly on the silicon. Silicon from the suicide and from the underlying junction dissolves in the aluminum, resulting in aluminum spikes through the underlying junction.
Another problem which is exacerbated by the shrinking device sizes is that of unreliable step coverage by the device metallization as it traverses steps in the device topography and especially as the metallization traverses into the contact openings. It is therefore especially beneficial if the contact metallization provides a relatively planar surface to which the interconnect metallization can be applied.
As shown in
FIG. 5A
, a conventional method of forming a contact is by sputtering a Ti/TiN layer
200
over the isolation layer
20
sidewalls of a contact opening
20
A and over a substrate surface. However the sputtered Ti/TiN layer
200
provides poor step coverage especially on the bottom.
As shown in
FIG. 5B
, the Ti/TiN layer
200
in the contact hole
20
A takes up space and makes filling the contact hole
20
A more difficult. The TiN layer
200
overhangs
215
the opening. This overhang
215
makes the void
211
problem in the metal plug
210
worse. Also, at the TiSix
214
at the bottom in incomplete thus causing high contact resistance and yield problems. At the corners, leakage
216
(Worm holes) also occur. WF
6
attacks the uncapped underlying Si to form worm holes
216
or insufficient corner coverage of TiN barrier results in formation of volatile TiF
4
gas and/or TiFx (x=1 to 3) higher resistance solid compound. The former TiF
4
will cause volcano formation and the latter (TiFx) leads to high resistance contacts.
The following U.S. patents show related processes and contact structures. U.S. Pat. No. 5.103,272 (Nishiyama) shows a TiSix layer and a TiN layer. The TiN layer is formed using an N
2
I/I. U.S. Pat. No. 4,851,369(Ellwanger et al.) forming an interconnect comprising a TiSix covered by a W plug. U.S. Pat. No. 5,545,592(Lacoponi) shows a method of forming a contact using a TiSix and a TiN layer. U.S. Pat. No. 4,926,237(Sun et al.) shows a contact using TiSix, TiN and a W plug.
There still exist a need for an improved contact method and structure.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a contact structure consisting of a silicon substrate, a titanium silicide layer, a barrier layer (TiN or TiNO layer), and a metal layer (e.g., Al or W).
It is an object of the present invention to provide a method for fabricating a contact structure consisting of a silicon substrate, a titanium silicide layer, a barrier layer (TiN or TiNO layer), and a metal layer (e.g., Al or W) wherein said titanium silicide layer is selectively deposited on the substrate surface.
It is another object of the present invention to provide a method for fabricating a contact structure consisting of a silicon substrate, a titanium silicide layer, a TiN barrier layer, and a metal layer (e.g., Al or W) wherein the TiN layer is formed by a self-aligned nitridation process.
It is another object of the present invention to provide a method for fabricating a contact structure consisting of a silicon substrate, a titanium silicide layer, a TiNO barrier layer, and a metal layer (e.g., Al or W) wherein the TiNO layer is formed by a nitration process using a N and O containing gas.
It is yet another object of the present invention to selectively form TiSi
2
on doped silicon regions and form TiN insitu so that the TiSix/TiN formation are performed in one reaction chamber.
It is yet another object of the present invention to form TiSi
2
and TiN over the doped Silicon areas and in salicided structures.
To accomplish the above objectives, the present invention provides a method of forming a contact structure comprising of: a silicon substrate, a titanium silicide layer, a barrier layer (i.e., TiN or TiNO), and a metal layer (e.g., Al or W). There are three embodiments of the invention for forming the titanium suicide layer and two embodiments for forming the barrier layer.
The first embodiment for forming selectively depositing a TiSix layer comprising the steps of:
a)
FIG. 1A
forming first insulating layer
20
having a contact opening
20
A on a substrate
10
;
b) FIG.
1
A—insitu clean the substrate
10
using of a gas selected from the group consisting of SiH
4
and H
2
for plasmaless cleaning or conventional dep dual frequency Ar or Ar/H
2
soft sputter etch cleaning;
c)
FIG. 1B
selectively depositing a first titanium silicide (TiSi
2
) layer
30
A at a lower TiCl4/SiH
4
flow ratio;
d) FIG.
1
C—selectively depositing a second titanium silicide (TiSi
2
) layer
30
B at a higher TiCl4/SiH
4
flow;
e) FIG.
1
D—selectively depositing a third titanium silicide TiSi
2
layer
30
C at an intermediate TiCl4/SiH
4
f
Ackerman Stephen B.
Booth Richard
Industrial Technology Research Institute
Lindsay Jr. Walter L.
Saile George O.
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