Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2006-11-28
2006-11-28
Mai, Son (Department: 2827)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S233100, C327S091000, C327S094000
Reexamination Certificate
active
07142462
ABSTRACT:
A receiving device which may include a plurality of pre-amplifiers and a plurality of samplers. Each of the plurality of samplers is connected to the output ports of a corresponding pre-amplifier. Each sampler samples data signals input thereto in response to a corresponding clock signal. The receiving device of a semiconductor memory unit may reduce input capacitance seen from the outside of chip and eliminate mutual interference of signals so as to prevent errors from being generated when data is extracted in the event of over sampling using pre-amplifiers. Furthermore, the receiving device can separately control the pre-amplifier for samplers that receive clock signals for data alignment and the pre-amplifier for samplers that accept clock signals for repeated data reception.
REFERENCES:
patent: 5355391 (1994-10-01), Horowitz et al.
patent: 6507224 (2003-01-01), Lee et al.
patent: 2004/0076228 (2004-04-01), Park et al.
patent: 2004/0202270 (2004-10-01), Lentine et al.
patent: 2004/0230388 (2004-11-01), Kim et al.
patent: 2005/0180498 (2005-08-01), Bhakta et al.
Mai Son
Volentine Francos & Whitt PLLC
LandOfFree
Input signal receiving device of semiconductor memory unit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Input signal receiving device of semiconductor memory unit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input signal receiving device of semiconductor memory unit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3654586