Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-08-28
2000-12-19
Iqbal, Nadeem
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
324763, G01R 3128
Patent
active
061638676
ABSTRACT:
A method and a system for testing integrated devices such as chips used on a printed circuit board. The system includes test logic formed on the chip and coupled to bi-directional input/output pads. The system is capable of testing input pads, output pads, and bi-directional pads by coupling an input test signal from one pad of a pair of pads to the output of a second pad of the pair of pads. If the signal read out of the second pad corresponds to the expected value, the pads may be considered properly connected. The chips may be tested at any stage during chip manufacture, including after forming the die on a wafer, after cutting the die from the wafer and after packaging the die to produce the chip, and after attaching the chip to a printed circuit board. The system and method allow for quick and easy testing of pad connectivity during the manufacturing process, while minimizing the number of extra gates and trace lines on the chip.
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Miller John
Ortiz Richard
Zhang Chenmin
Hewlett--Packard Company
Iqbal Nadeem
LandOfFree
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