Input/output data pipeline circuit of semiconductor memory...

Details Input/output data pipeline circuit of semiconductor memory... Input/output data pipeline circuit of semiconductor memory...

2007-09-04

2007-09-04

Bragdon, Reginald (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S167000, C711S168000, C365S189050

Reexamination Certificate

active

10786471

ABSTRACT:
An input/output data pipeline circuit of a semiconductor memory device includes a first transmitting unit, a control signal generating unit, and a second transmitting unit. The first transmitting unit receives data stored in a memory cell and transmits data to an input/output driver in response to activation of a first switching signal and a second switching signal. The control signal generating unit receives a clock signal from the semiconductor memory device and, corresponding to the frequency of the clock signal, outputs a control signal, the first switching signal, and the second switching signal. The second transmitting unit transmits data to the input/output driver in response to activation of the control signal. The first transmitting unit and the second transmitting unit are alternatively activated.

REFERENCES:
patent: 6263448 (2001-07-01), Tsern et al.
patent: 6359831 (2002-03-01), McLaury
patent: 6363465 (2002-03-01), Toda
patent: 6606300 (2003-08-01), Blanc et al.

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