Input/output circuits and methods for testing integrated circuit

Details Input/output circuits and methods for testing integrated circuit Input/output circuits and methods for testing integrated circuit

1998-05-06

1999-11-16

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Testing

36518901, 36518902, 36518903, 36518905, G11C 700, G11C 2900

Patent

active

059869534

ABSTRACT:
Integrated circuit memory devices include a plurality of pads that receive signals from external of the memory device and a plurality of data buses, a respective one of which is operatively connected to a respective one of the plurality of pads. A plurality of multiplexers is provided, a respective one of which is operatively connected to a respective one of the pads and to each of the data buses, to write data from the data buses to the memory cell in a direct access test mode, and to write data from the respective one of the pads to the memory cell array in a normal mode. The integrated circuit memory devices also preferably include a plurality of input/output devices, a respective one of which operatively connects the respective one of the pads to the respective one of the multiplexers. The plurality of input/output devices preferably are a plurality of pipelines that store signals that are serially received from external of the memory device, and that provide the stored signals to the multiplexers.

REFERENCES:
patent: 5260906 (1993-11-01), Mizukami
patent: 5367492 (1994-11-01), Kawamoto et al.
patent: 5379308 (1995-01-01), Nguyen et al.
patent: 5506499 (1996-04-01), Puar
patent: 5568437 (1996-10-01), Jamal
patent: 5577052 (1996-11-01), Morris
patent: 5592422 (1997-01-01), McClure
patent: 5659514 (1997-08-01), Hazani
patent: 5677885 (1997-10-01), Roohparvar
patent: 5793685 (1998-08-01), Suma

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