Input/output buffer test circuitry and leads additional to...

Details Input/output buffer test circuitry and leads additional to... Input/output buffer test circuitry and leads additional to...

2007-06-07

2008-11-11

Lamarre, Guy J (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

07451370

ABSTRACT:
Peripheral input and output buffer circuitry is tested using scan path circuitry selectively connecting external signals TSA, TSB, and TSC to the buffer circuitry. This is in addition to testing the internal circuitry of the integrated circuit with the scan path circuitry. An external signal, TSC, provides a load to the output of the buffer circuitry. An external signal, TSA, receives a response from input buffer circuitry and supplies a stimulus signal to output buffer circuitry. An external signal, TSB, receives a response signal from output buffer circuitry and supplies a stimulus signal to input buffer circuitry. This avoids a wafer tester having to contact bond pads connected to the buffer circuitry.

REFERENCES:
patent: 4875003 (1989-10-01), Burke
patent: 5115191 (1992-05-01), Yoshimori
patent: 5519355 (1996-05-01), Nguyen
patent: 5736849 (1998-04-01), Terayama
patent: 5938783 (1999-08-01), Whetsel

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