Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-09-26
2004-11-09
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189040
Reexamination Certificate
active
06816417
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an input/output buffer circuit suitable for use in a microcomputer or the like, which controls an external bus connected to an input/output terminal.
A microcomputer or the like is provided with an input/output buffer circuit for controlling an external bus. The input/output buffer circuit is connected to a data bus connected to an input/output terminal and mainly controlled by a read enable signal RD and a write enable signal WR. Since the data bus is a bidirectional bus, it needs to be placed under input/output control.
In general, a read enable signal RD or a timing signal similar thereto is used as an input-permitting control signal. Further, a write enable signal WR or a timing signal similar thereto is used as an output-permitting control signal. There might be a case in which a write enable signal WR or a timing signal similar thereto is used only as a control signal for always allowing the input and output without using a control signal for allowing the input.
Since, however, the write enable signal WR or timing signal similar thereto used as the output-permitting control signal is not active in the input/output buffer circuit having the above configuration during its access-to-outside free time, the output of the data bus results in high impedance Hiz. Since the read enable signal RD becomes negative when the write enable signal WR is active, the data bus is brought to the high impedance Hiz when no output is transferred even from an external part connected to the input/output terminal.
General externally connected parts might include one in which a through current flows in an input gate thereof when a data bus connected to an input/output terminal on the microcomputer side is brought to the high impedance Hiz. Therefore, a problem arises in that a system including the microcomputer and the externally connected parts increases in current consumption. This becomes a big problem in a low power consumption mode for bringing a clock to a halt in particular. As a measure against it, a measure might be taken for pulling up or down the data bus or externally providing a bus hold circuit so as to prevent the data bus from being brought to the high impedance Hiz. However, the measure involves a problem in that current consumption at the operation of the data bus increases in reverse.
SUMMARY OF THE INVENTION
The present invention may provide an input/output buffer circuit capable of suppressing an increase in current consumption of the whole system even in a low power consumption mode for bringing a clock to halt.
The input/output buffer circuit according to the invention of the present application has an input/output terminal for performing the input/output of data, and outputs a signal to the input/output terminal when a write enable signal is in an active state and receives data from the input/output terminal when a read enable signal is in an active state.
The input/output buffer circuit according to the invention of the present application outputs a signal based on any of signals supplied thereto when the write enable signal and the read enable signal are both in a non-active state.
REFERENCES:
patent: 5278789 (1994-01-01), Inoue et al.
Le Thong Q.
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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