Input circuit for memory device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

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C365S189020

Reexamination Certificate

active

07369448

ABSTRACT:
An input circuit for a semiconductor memory device is disclosed. The input circuit controlling transmission paths for data having passed through a data input buffer by using a 1-clock shifted block column address is provided. In particular, a data input apparatus improving a data processing speed by advancing an operation time point of a data bus writer is provided.

REFERENCES:
patent: 5198999 (1993-03-01), Abe et al.
patent: 6292428 (2001-09-01), Tomita et al.
patent: 6320819 (2001-11-01), Tomita et al.
patent: 7184325 (2007-02-01), Lee
patent: 2006/0067151 (2006-03-01), Miyamoto

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