Input circuit for a memory device, and a memory device and...

Details Input circuit for a memory device, and a memory device and... Input circuit for a memory device, and a memory device and...

2006-01-05

2008-08-26

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including signal comparison

C365S201000, C365S189090

Reexamination Certificate

active

07417902

ABSTRACT:
In one embodiment, the input circuit includes a receiver circuit that generates a data signal based on a pair of differential data signals. A detecting circuit detects an offset voltage between the pair of differential data signals, and an adjusting circuit adjusts operation of the receiver to reduce a magnitude of the detected offset voltage based on the detected offset voltage.

REFERENCES:
patent: 5287063 (1994-02-01), Izawa
patent: 5821795 (1998-10-01), Yasuda et al.
patent: 6282210 (2001-08-01), Rapport et al.
patent: 6459620 (2002-10-01), Eshel
patent: 6662304 (2003-12-01), Keeth et al.
patent: 6826390 (2004-11-01), Tamura

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