Input buffer circuit, input/output buffer circuit and portable s

Details Input buffer circuit, input/output buffer circuit and portable s Input buffer circuit, input/output buffer circuit and portable s

1991-11-14

1994-05-03

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365228, 365229, G11C 1400, H03K 301

Patent

active

053093968

ABSTRACT:
An input buffer circuit includes at least one unidirectional buffer, a first power supply line for supplying power to the buffer, a power cutoff circuit connected between the buffer and the first power supply line for connecting the first power supply line to the buffer when a predetermined voltage level is supplied to the first power supply line, and for disconnecting the first power supply line from the buffer when the predetermined voltage level is not supplied to the first power supply line, an impedance lowering circuit for lowering impedance of an input bus when the predetermined level of power is not supplied to the first power supply line, and a second power supply line for supplying power to the impedance lowering circuit. Insertion of the input buffer circuit in the input bus of a semiconductor memory suppresses the current consumed by the memory and improves the reliability of the memory.

REFERENCES:
patent: 4730121 (1988-03-01), Lee et al.
patent: 5016223 (1991-05-01), Kimura et al.
patent: 5101119 (1992-03-01), Yoshimori et al.
patent: 5168206 (1992-12-01), Jones
patent: 5197026 (1993-03-01), Butler
patent: 5212664 (1993-05-01), Shinohara

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