Input buffer circuit

Details Input buffer circuit Input buffer circuit

2000-05-19

2002-02-19

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S115000, C326S121000

Reexamination Certificate

active

06348815

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to an input buffer circuit in a semiconductor device.
2. Description of the Related Art
A clock signal typically has the highest operational frequency of any of the signals input into a semiconductor device, and the operational frequency of the clock signal increases with an increase in the operational speed of a system connected to the semiconductor device. Thus, semiconductor devices require a fast input buffer circuit to accept the clock signal.
FIG. 1
is a circuit diagram of a conventional input buffer circuit for a clock signal. Referring to
FIG. 1
, the conventional input buffer circuit includes a differential amplifier
11
and a buffer. The differential amplifier
11
uses a reference voltage VREF and in response to an input clock signal CLK, generates a signal OUTB having a phase that is approximately opposite to the phase of the clock signal CLK. The differential amplifier
11
outputs the signal OUTB from a node A in differential amplifier
11
, to the buffer
13
. The buffer
13
buffers the signal OUTB and changes the voltage level of the signal OUTB to output a CMOS-level signal DCLKB.
To operate the conventional input buffer circuit at a high frequency, a DC current through the differential amplifier
11
is increased by decreasing the resistance of a resistor R. Reducing the resistance R increases current that charges and discharges the node in the differential amplifier
11
when the input clock signal CLK changes voltage levels. However, when the DC current increases, power consumption increases. Also, the transconductance of a short-channel transistor is independent of the level of current and is proportional to the width of a channel, so that the operation speed does not increase past a certain critical point even if the resistance of the resistor R is zero.
SUMMARY OF THE INVENTION
An embodiment of the present invention provides an input buffer circuit that consumes a small amount of power and operates quickly. The input buffer circuit includes a differential amplifier, a buffer, and a switched current path (typically including a current source and/or a current sink). The differential amplifier receives an input signal and a reference voltage and outputs an internal signal having a phase approximately opposite to the phase of the input signal. The current source conducts a charging current to the differential amplifier to reduce the time required for the internal signal to transit from a logic “low” level to a logic “high” level. The current sink conducts a discharging current from the differential amplifier to reduce the time required for the internal signal to transit from the logic “high” level to the logic “low” level. In one embodiment, the input buffer circuit includes only one of the current source and the current sink in the switched current path.
In one embodiment, the differential amplifier includes a differential amplification unit for generating the internal signal in response to the input signal and the reference voltage, and a resistive device between one end of the differential amplification unit and ground.
According to one embodiment, the current source is between a power supply voltage and the node in the differential amplifier, and supplies a current to the node for a predetermined short period of time following the falling edge of the input signal. The current sink is between the differential amplification unit and ground and discharges a current from the differential amplification unit for a short period of time following the rising edge of the input signal.
According to another embodiment, the current source is between a power supply voltage and the node in the differential amplifier, and the current sink is between the node of the differential amplifier and ground. The current sink thus directly discharges a current from the node in the differential amplifier to ground for the short period of time following the rising edge of the input signal.
In the above embodiments, the current source can include first and second PMOS transistors connected in series between the power supply voltage and the output node of the differential amplifier. The output signal of the buffer is applied to the gate of the first PMOS transistor, and the input signal is applied to the gate of the second PMOS transistor.
The current sink includes first and second NMOS transistors connected in series between the differential amplifier and the ground voltage. The input signal is applied to the gate of the first NMOS transistor, and the output signal of the buffer is applied to the gate of the second NMOS transistor. The current sink can connect to an end of the differential amplifier or directly to the node in the differential amplifier.


REFERENCES:
patent: 5736871 (1998-04-01), Goto
patent: 5834974 (1998-11-01), Kim
patent: 5990708 (1999-11-01), Hu
patent: 5999020 (1999-12-01), Volk et al.
patent: 6121812 (2000-09-01), Tsukikawa
patent: 6184744 (2001-02-01), Morishita
patent: 0729226 (1996-08-01), None
patent: 08237103 (1996-09-01), None
patent: 08298445 (1996-11-01), None

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