Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
2007-08-16
2009-12-08
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C326S082000, C326S091000
Reexamination Certificate
active
07629810
ABSTRACT:
Stable testing is performed on an input and output circuit. An output stage outputting output signal to input/output terminal DQ comprises: a differential pair formed from an Nch transistor N1, having as load a Pch transistor P1and resistance element R1, and an Nch transistor N2, having as load a Pch transistor P2and resistance element R2; and an Nch transistor N3supplying operating current to the differential pair. The input/output terminal DQ is connected to the drain of the Nch transistor N1. The output stage is operated as differential pair, in the normal operation mode (TM=L), wherein the Pch transistors P1, P2are ON, a read-data signal RD is supplied to the differential pair, and a specified voltage CC is supplied to the gate of the Nch transistor N3; and in the test mode (TM=H), a CMOS circuit is established wherein a read-data signal RD is supplied to the gate of the Pch transistor P1and the gate of the Nch transistor N3, turning the Nch transistor N1ON.
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Cho James H.
Elpida Memory Inc.
Hammond Crystal L
Scully , Scott, Murphy & Presser, P.C.
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