Innovative narrow gate formation for floating gate flash...

Details Innovative narrow gate formation for floating gate flash... Innovative narrow gate formation for floating gate flash...

2002-06-24

2003-06-24

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S952000

Reexamination Certificate

active

06583009

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to stacked gate memory devices such as an array of flash memory cells, and relates more particularly to a method of forming a stacked gate flash memory cell having a feature dimension which may be less than a feature dimension capable of being formed using conventional lithography processes.
BACKGROUND OF THE INVENTION
As is generally known, in recent years a new category of electrically erasable EPROMs/EEPROMs has emerged as an important non-volatile memory which combines the advantages of EPROM density with EEPROM electrical erasability and are sometimes referred to as “flash” EPROM or EEPROM. Flash memory devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, as illustrated in prior art
FIG. 1A
, a memory device such as a flash memory
10
comprises one or more high density core regions
11
and a low density peripheral portion
12
on a single substrate
13
. The high density core regions
11
typically consist of at least one M×N array of individually addressable, substantially identical floating-gate type memory cells and the low density peripheral portion
12
typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to effect designated operations of the cell such as programming, reading or erasing).
The memory cells within the core portion
11
are coupled together in a NOR-type circuit configuration, such as, for example, the configuration illustrated in prior art FIG.
1
B. Each memory cell
14
has a drain
14
a
, a source
14
b
and a stacked gate
14
c.
The NOR configuration illustrated in
FIG. 1B
has each drain terminal
14
a
of the transistors within a single column connected to the same bit line (BL). In addition, each flash cell
14
has its stacked gate terminal
14
c
coupled to a different word line (WL) while all the flash cells in the array have their source terminals
14
b
coupled to a common source terminal (CS). In operation, individual flash cells may be individually addressed via the respective bit line and word line using peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
Prior art
FIG. 1C
represents a fragmentary cross section diagram of a typical memory cell
14
in the core region
11
of prior art
FIGS. 1A and 1B
. Such a cell
14
typically includes the source
14
b
, the drain
14
a
, and a channel
15
in a substrate or P-well
16
; and the stacked gate structure
14
c
overlying the channel
15
. The stacked gate
14
c
further includes a thin gate dielectric layer
17
a
(commonly referred to as the tunnel oxide) formed on the surface of the P-well
16
. The stacked gate
14
c
also includes a polysilicon floating gate
17
b
which overlies the tunnel oxide
17
a
and an interpoly dielectric layer
17
c
overlies the floating gate
17
b
. The interpoly dielectric layer
17
c
is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate
17
d
overlies the interpoly dielectric layer
17
c
. The control gates
17
d
of the respective cells
14
that are formed in a lateral row share a common word line (WL) associated with the row of cells (see, e.g., prior art FIG.
1
B). In addition, as highlighted above, the drain regions
14
a
of the respective cells in a vertical column are connected together by a conductive bit line (BL). The channel
15
of the cell
14
conducts current between the source
14
b
and the drain
14
a
in accordance with an electric field developed in the channel
15
by the stacked gate structure
14
c.
According to conventional operation, the flash memory cell
14
operates in the following manner. The cell
14
is programmed by applying a relatively high voltage V
G
(e.g., approximately 9 volts) to the control gate
17
d
and connecting the source to ground and the drain
14
a
to a predetermined potential above the source
14
b
(e.g., approximately 5 volts). These voltages generate a vertical and lateral electric field along the length of the channel from the source to the drain. This electric field causes electrons to be drawn off the source and begin accelerating toward the drain. As they move along the length of the channel, they gain energy. If they gain enough energy, they are able to jump over the potential barrier of the oxide into the floating gate
17
b
and become trapped in the floating gate
17
b
since the floating gate
17
b
is surrounded by insulators (the interpoly dielectric
17
c
and the tunnel oxide
17
a
). As a result of the trapped electrons, the threshold voltage of the cell
14
increases, for example, by about 2 to 5 volts. This change in the threshold voltage (and thereby the channel conductance) of the cell
14
created by the trapped electrons is what causes the cell to be programmed.
To read the memory cell
14
, a predetermined voltage V
G
that is greater than the threshold voltage of an unprogrammed or erased cell, but less than the threshold voltage of a programmed cell, is applied to the control gate
17
d
with a voltage applied between the source
14
b
and the drain
14
a
(e.g., tying the source
14
b
to ground and applying about 12 volts to the drain
14
a
). If the cell
14
conducts (e.g., about 50-100 &mgr;A), then the cell
14
has not been programmed (the cell
14
is therefore at a first logic state, e.g., a zero “0”). Likewise, if the cell
14
does not conduct (e.g., considerably less current than 50-100 &mgr;A), then the cell
14
has been programmed (the cell
14
is therefore at a second logic state, e.g., a one “1”). Consequently, one can read each cell
14
to determine whether it has been programmed (and therefore identify its logic state).
A flash memory cell
14
can be erased in a number of ways. In one arrangement, a relatively high voltage VS (e.g., approximately 12-20 volts) is applied to the source
14
b
and the control gate
17
d
is held at a ground potential (V
G
=0), while the drain
14
a
is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide
17
a
between the floating gate
17
b
and the source
14
b
. The electrons that are trapped in the floating gate undergo Fowler-Nordheim tunneling through the tunnel oxide
17
a
to the source
14
b
. In another arrangement, applying a negative voltage on the order of minus 10 volts to the control gate, applying 5 volts to the source and allowing the drain to float can also erase a cell. In a further arrangement, applying 5 volts to the P-well and minus 10 volts to the control gate while allowing the source and drain to float erases a cell.
In order to reduce memory costs, designers are constantly seeking ways to reduce a size of an individual flash memory cell in order to increase the memory density and therefore decrease the unit cost per bit. Unfortunately, a size of a flash memory cell is often limited by the lithography capabilities of the manufacturing process. For example, as illustrated in
FIG. 1C
, a width
19
of the stacked gate cell is limited by the lithography resolution of the stepper system. For example, in present day manufacturing processes, a feature dimension can be produced reliably at a feature size of about 0.13 micron. In order to further reduce cell size and therefore increase memory density and decrease the unit cost per bit, it would be desirable to create a memory cell having a width that is less than the capability of present day lithography processes, for example, of a dimension of about 100 nm (0.10 micron) or less.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exten

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