Initialization of non-volatile programmable latches in circuits

Details Initialization of non-volatile programmable latches in circuits Initialization of non-volatile programmable latches in circuits

1998-10-23

2000-07-04

Nelms, David

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

3652257, 365233, G11C 1604

Patent

active

060848030

ABSTRACT:
A non-volatile programmable latch (110) in an integrated circuit (310) is initialized by an initialization signal (SET). At least a portion of the initialization signal is generated in response to a command to the circuit to perform a circuit initialization operation. In some embodiments, the circuit is a synchronous dynamic random access memory (SDRAM), or a synchronous graphics random access memory (SGRAM). The command is a mode register set command (MRS). The command is received when a predetermined period of time has elapsed after power was turned on. Waiting for the predetermined period of time before initializing the latch allows the voltage powering the latch to develop so that the latch can be initialized reliably.

REFERENCES:
patent: 4387503 (1983-06-01), Aswell et al.
patent: 4404635 (1983-09-01), Flaker
patent: 4532402 (1985-07-01), Overbeck
patent: 4532607 (1985-07-01), Uchida
patent: 4546455 (1985-10-01), Iwahashi et al.
patent: 4614881 (1986-09-01), Yoshida et al.
patent: 4617651 (1986-10-01), Ip et al.
patent: 4725979 (1988-02-01), Hoberman
patent: 4771285 (1988-09-01), Agrawal et al.
patent: 4779229 (1988-10-01), Agrawal
patent: 4837520 (1989-06-01), Golke et al.
patent: 4852044 (1989-07-01), Turner et al.
patent: 4943804 (1990-07-01), Lee et al.
patent: 5066998 (1991-11-01), Fischer et al.
patent: 5086331 (1992-02-01), Hartgring et al.
patent: 5134585 (1992-07-01), Murakami et al.
patent: 5185291 (1993-02-01), Fischer et al.
patent: 5285953 (1994-02-01), Tsujimoto
patent: 5440246 (1995-08-01), Murray et al.
patent: 5459684 (1995-10-01), Nakamura et al.
patent: 5497355 (1996-03-01), Mills et al.
patent: 5506638 (1996-04-01), Cowles et al.
patent: 5526320 (1996-06-01), Zagar et al.
patent: 5544124 (1996-08-01), Zagar et al.
patent: 5566107 (1996-10-01), Gilliam
patent: 5640364 (1997-06-01), Merritt et al.
patent: 5710741 (1998-01-01), McLaury
patent: 5793688 (1998-08-01), McLaury
patent: 5812489 (1998-09-01), Matsui
patent: 5870342 (1999-02-01), Fukuda
patent: 5898621 (1999-04-01), Takahashi et al.
B. Prince, "High Performance Memories" New Architecture DRAMs and SRAMs Evolution and Function, 1996, pp. 135-227.
B. Prince, "Semiconductor Memories" A Handbook of Design, Manufacture and Application, Second Edition, (1991), pp. 762-764.
"Synchronous Graphics RAM" Micron Technology, Inc. of Boise Idaho, 1998, pp. 1-45.

Affiliated with

Also associated with

Rating

Initialization of non-volatile programmable latches in circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Initialization of non-volatile programmable latches in circuits , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Initialization of non-volatile programmable latches in circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1492431