Inhibit and transfer circuitry for memory cell being read from m

Details Inhibit and transfer circuitry for memory cell being read from m Inhibit and transfer circuitry for memory cell being read from m

1986-04-15

1988-05-03

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365195, 365203, G11C 700

Patent

active

047424877

ABSTRACT:
An inhibit and transfer circuit for a memory system having multiple read ports. Bit lines are precharged. In a reading operation, the precharging is disconnected at the same time that the bit lines are selectively connected to one or more sense latches, associated with multiple reading ports. Feedback paths in the sense latches are disconnected during the reading. The selection of the sense latches to which the bit lines are coupled is determined by a comparison of multiple addressing signals.

REFERENCES:
patent: 4535428 (1985-08-01), Furman
patent: 4577292 (1986-03-01), Bernstein
patent: 4598387 (1986-07-01), Chuang et al.
patent: 4616342 (1986-10-01), Miyamoto
patent: 4616347 (1986-10-01), Bernstein

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