Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-08-19
2002-11-12
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C714S004110
Reexamination Certificate
active
06480923
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to information processing systems and more particularly to an improved information transfer system in a computer related environment.
BACKGROUND OF THE INVENTION
As computer systems and networked computer systems proliferate, and become integrated into more and more information processing systems which are vital to businesses and industries, there is an increasing need for faster information processing and increased data handling capacity. Even with the relatively rapid state-of-the-art advances in processor technology, and the resulting increased processor speeds, a need still exists for faster processors and increased system speeds and bandwidths. As new applications for computers are implemented, new programs are developed and those programs are enriched with new capabilities almost on a daily basis. While such rapid development is highly desirable, there is a capability cost in terms of system speed and bandwidth.
As used herein, the term “bandwidth” is used generally to refer to the amount of information that can be transferred in a given period of time. In transferring information between devices in a computer system, information is frequently temporarily stored in “holding” buffers along the path of the information transfer. Such buffers include bridge buffers which are generally located in bridge circuits connecting devices or busses between which the information is to be transferred. In one example, peripheral component interconnect or “PCI” system bridge circuit buffers are assigned to PCI devices, which are installed in PCI “slots” and coupled to an associated PCI bus. Complex computer systems may include many bridge circuits connected between individual PCI busses or connecting a PCI bus to a system bus. In a PCI system, any of the computer system enhancement devices or adapters are generally included on one or more circuit boards which are mounted or inserted into PCI “slots”, i.e. into board connector terminals mounted on a system motherboard.
Standard PCI-PCI bridges are utilized in the industry today as a means to provide added slots for PCI devices since individual PCI busses are limited to 10 loads per bus at 33 MHz and 5 loads at 66 MHz (a soldered device counts as one load and a slotted device counts as two loads). This requires a combination of multiple PCI host bridges and/or multiple standard PCI-PCI bridges per each server drawer where server drawers typically house 14-16 PCI slots per drawer. The total integrated circuit (IC) or chip and packaging cost is expensive utilizing standard components.
Thus, there is an increasing need for an improved computer system which is designed to be able to efficiently handle greater numbers of peripheral adapters in computer systems.
SUMMARY OF THE INVENTION
A method and implementing system is provided for defining and managing bridge buffers for a PCI-to-PCI bridge and PCI bus router system. An operating methodology is implemented to satisfy a merging of PCI requirements and multi-node router or switching requirements. In an exemplary embodiment, each bridge buffer set can contain transaction requests that are going in the same direction, and transaction completions that are going in the same direction, and a mix of both requests and completions that are going in different directions. Buffers are renamed rather than moving delayed requests to an opposing path when converted to a completion transaction. Further, transactions flowing between any two given nodes have no ordering requirements relative to transactions between other nodes thereby providing an independent non-blocking operation.
REFERENCES:
patent: 5592610 (1997-01-01), Chittor
patent: 5898826 (1999-04-01), Pierce et al.
patent: 6233641 (2001-05-01), Graham et al.
Moertl Daniel Frank
Neal Danny Marvin
Thurber Steven Mark
Yanes Adalberto Guillermo
Dharia Rupal
McBurney Mark E.
Wilder Robert V.
LandOfFree
Information routing for transfer buffers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Information routing for transfer buffers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Information routing for transfer buffers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2967743