Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-02-09
2001-09-18
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S145000, C711S127000
Reexamination Certificate
active
06292870
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an information processing system, or more particularly, to an information processing system in which memory devices and copies of tags are accessed in response to access requests issued from a plurality of processing units.
2. Description of the Related Art
In recent years, an art for enabling an information processing system to operate at a high speed using as small a number of logic devices, and as little wiring, as possible has been demanded in conformity with the trend toward a higher density of components and a higher operating speed.
A control sequence for controlling access to memories or memory access in a known information processing system will be described.
The known information processing system comprises a plurality of processing units, memory devices, tag RAMs, and a system controller. Each processing unit has a cache memory and a tag RAM. In the tag RAMs, copies of tags of all the processing units are stored.
When each processing unit accesses a memory, first, the processing unit attempts to index and update the contents of its own tag. If desired data is stored in its own cache memory, the processing unit accesses the cache memory. If the desired data is not stored in its own cache memory, the processing unit issues a memory access request to the system controller. The system controller indexes and updates the copies of tags stored in the tag RAM. If it is found as a result of indexing that the desired data is not stored in any other processing unit, access to memory, or a memory access, is needed. The memory device is therefore activated.
In the known information processing system, as the number of processing units increases, the competition among the processing units for a memory access control unit becomes fierce. Consequently, the efficiency of memory access deteriorates.
SUMMARY OF THE INVENTION
The present invention attempts to solve the above problem. An object of the present invention is to provide an information processing system including a plurality of processing units each having a cache memory while improving the efficiency of access to memories, or memory access, using a simple circuit.
The present invention attempts to accomplish the above object. According to the present invention, there is provided an information processing system in which: processing units having memories and a system controller are interconnected over a bus; the system controller includes access control units for controlling access to copies of tags of the first memories in the processing units and access to memory devices; and thus controls access to memories, or memory access, gained by the processing units. A plurality of memory interfaces are included for making it possible to access the memory devices on an interleaved basis. A term “way” is used for distinguish each of the memory devices on an interleaved basis. Furthermore, the same numbers of copies of tags and memory access control units as the number of the memory interfaces are included for making it possible to access the tags on an interleaved basis.
Since it becomes possible to access memories or tags on an interleaved basis, even if the number of processing units increases, competition for the memory access control units subsides. Consequently, the performance of memory access can be improved.
Moreover, according to the present invention, the memory access control units may each include a means for varying the number of ways permitting interleaving of the second memories. This makes it possible to set the number of memory devices to be mounted in one information processing system to any value.
When the number of ways leading to memories is varied, the number of ways permitting interleaving of tags may be varied or fixed. When the number of ways leading to tags is fixed, even if the memory access control units decrease the number of ways permitting interleaving of the second memories, the memory access control units do not decrease the number of circuits to be operated among all the circuits for enabling access to the tags or tag access.
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Ishizuka Takaharu
Noda Takato
Shibata Yasuhide
Sugano Fumitake
Takeno Takumi
Fijitsu Limited
Peikari B. James
Staas & Halsey , LLP
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