Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-04-30
2001-01-23
Beausoliel, Jr., Robert W. (Department: 2785)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
06178524
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the testing of information processing system hardware and more particularly, but not exclusively to Power-on Self Test (POST) of computer hardware.
BACKGROUND OF THE INVENTION
It is common practice during the initialisation of information processing systems such as computers, controller cards etc to carry out a series of tests on various components of the system hardware in order to determine that everything is in working order i.e. that an application designed to run on the hardware will function correctly. This type of testing is commonly referred to as Power-on Self Test (POST) and is carried out when the system is powered-on or otherwise reset. Traditionally POST code is provided in read-only memory in the system and runs as a completely separate program from the main application which subsequently runs on the same hardware. Typically, the POST code is designed to thoroughly test, in sequence, the operation of a number of critical hardware components. POST either terminates successfully or fails with some diagnostic code.
Coupling between the POST and the application is normally very poor in that failure of POST normally means that the application code never runs. This is because the application is assumed to be intolerant of bad hardware.
It would be desirable to provide a technique which is suitable for more closely coupling the POST and application and which allows for continued operation of the system in the event of non-critical failures detected during POST.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, there is provided an information processing system including a plurality of hardware component types, each type including one or more members, the system further including software for controlling the operation of the hardware, the software being arranged such that each component type has associated therewith a software class which defines a constructor for creating one or more instances of the class, each instance corresponding to one member of the hardware type, the constructor for each software class further including or referencing program code for testing the operation of each hardware member of the associated hardware type.
Thus the present invention provides a system in which software classes are defined for each type of hardware component. Each class defines a constructor for creating one or more instances (objects) of the class, each instance corresponding to a member of the software type. The constructor further includes or references test code for testing the operation of the hardware member associated with the instance under construction. By providing local test code for a constructor, the associated hardware component can be tested more locally than is the case with the prior art POST operation where the test code for the various components is kept separate from the control code.
The present invention is applicable to systems incorporating different numbers of hardware component types. In one example, the system includes at least first and second hardware types, the second hardware type being a subcomponent of the first hardware type; the control software including first and second software classes associated with the first and second hardware types. In such a system, it is advantageous for the constructor defined for the first software class to be designed to call the constructor defined for the second software class to initiate construction of the one or more instances of the second software class corresponding to the one or more members of the second hardware type.
For example, as will be described below with reference to the preferred embodiments, the plurality of different hardware types may include a controller chip and a chip port. There may be one controller chip which includes two chip ports. A software class is defined for the chip and for the chip port. In operation, the chip constructor calls the chip port constructor which constructs two instances of the chip port class, one instance for each chip port present in the controller chip. Once the construction of each chip port instance is complete, the test code defined in the chip port constructor will test each chip port to determine whether it is operational. In accordance with one particular advantage of the present invention, if a failure is detected during the operation of the chip port, this error is reported back (e.g. in the form of an exception thrown by the chip port constructor) to the chip constructor. The chip constructor will then include the means for handling the error (catching the exception) e.g. by deciding whether the system can operate without the failed component.
In this way a component failure does not necessarily result in a failure of the complete system.
The present invention also provides a method of operating an information processing system having a plurality of hardware component types, each type including one or more members, the system further including software for controlling the operation of the hardware, the software being arranged such that each component type has associated therewith a software class which defines a constructor for creating one or more instances of the class, each instance corresponding to one member of the hardware type; the method comprising constructing the one or more class instances, and for each instance, executing program code for testing the operation of each hardware member of the associated hardware type, the test code being included in or referenced by the associated constructor.
A preferred embodiment of the present invention will now be described, by way of example only, with reference to the accompanying drawings.
REFERENCES:
patent: 5337262 (1994-08-01), Luthi et al.
patent: 5606661 (1997-02-01), Wear et al.
patent: 5675748 (1997-10-01), Ross
patent: 5805796 (1998-09-01), Finch et al.
patent: 5848236 (1998-12-01), Dearth et al.
patent: WO 95/28047 (1995-10-01), None
Baderman Scott T.
Beausoliel, Jr. Robert W.
Cameron Douglas W.
Dougherty Anne Vachon
International Business Machines Corp.
LandOfFree
Information processing system hardware test does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Information processing system hardware test, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Information processing system hardware test will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2542493