Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
Patent
1995-11-13
1999-04-27
Bragdon, Reginald G.
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
Addressing cache memories
711128, 711136, 711122, G06F 1208
Patent
active
058976515
ABSTRACT:
An information handling system includes a cache memory architecture which includes a means for performing a direct lookup by identifying the double word in the cache using the congruence class ID field, a set ID field and a double word ID field of the request address, and sending the double word to the CPU, and if the tag of the identified double word does not match the tag of the request address, sending a cancel signal to the CPU, and the double word with a matched tag in the congruence class, and if no match occurs, reloading the line l1 into the improved cache from a lower level cache or from main memory. The line in the set identified by the set ID field replaces the least recently used line in the congruence class and its place is taken by the missing line.
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Cheong Hoichi
So Kimming
Bragdon Reginald G.
Dillion Andrew J.
England Anthony V.S.
International Business Machines - Corporation
Virga Philip T.
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