Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-12-13
2001-10-09
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C118S7230AN, C118S716000, C427S455000, C427S456000, C427S099300, C427S123000, C427S124000, C427S576000, C438S597000, C438S676000, C438S679000
Reexamination Certificate
active
06300245
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates generally to semiconductor integrated circuits, and more particularly, to an apparatus and method for fabricating a spherical-shaped semiconductor integrated circuit.
Conventional integrated circuits, or “chips,” are formed from a flat surface semiconductor wafer. The semiconductor wafer is first manufactured in a semiconductor material manufacturing facility and is then provided to a fabrication facility. At the latter facility, several layers are processed onto the semiconductor wafer surface. Once completed, the wafer is then cut into one or more chips and assembled into packages. Although the processed chip includes several layers fabricated thereon, the chip still remains relatively flat.
A fabrication facility is relatively expensive due to the enormous effort and expense required for creating flat silicon wafers and chips. For example, manufacturing the wafers requires several high-precision steps including creating rod-form polycrystalline semiconductor material; precisely cutting ingots from the semiconductor rods; cleaning and drying the cut ingots; manufacturing a large single crystal from the ingots by melting them in a quartz crucible; grinding, etching, and cleaning the surface of the crystal; cutting, lapping and polishing wafers from the crystal; and heat processing the wafers. Moreover, the wafers produced by the above processes typically have many defects which are largely attributable to the difficulty in making a single, highly pure crystal due to the above cutting, grinding and cleaning processes as well as due to the impurities, including oxygen, associated with containers used in forming the circuits formed on these wafers become smaller.
Another major problem associated with modern fabrication facilities for flat chips is that they require extensive and expensive equipment. For example, dust-free clean rooms and temperature-controlled manufacturing and storage areas are necessary to prevent the wafers and chips from defecting and warping. Also, these types of fabrication facilities suffer from a relatively inefficient throughput as well as an inefficient use of the silicon. For example, facilities using in-batch manufacturing, where the wafers are processed by lots, must maintain huge inventories to efficiently utilize all the equipment of the facility. Also, because the wafers are round, and the completed chips are rectangular, the peripheral portion of each wafer cannot be used.
Still another problem associated with modern fabrication facilities is that they do not produce chips that are ready to use. Instead, there are many additional steps that must be completed, including cutting and separating the chip from the wafer: assembling the chip to a lead frame which includes wire bonding, plastic or ceramic molding and cutting and forming the leads, positioning the assembled chip onto a printed circuit board; and mounting the assembled chip to the printed circuit board. The cutting and assembly steps introduce many errors and defects due to the precise requirements of such operations. In addition, the positioning and mounting steps are naturally two-dimensional in character, and therefore do not support curved or three dimensional areas.
Therefore, due to these and various other problems, only a few companies in the world only can successfully manufacture conventional flat chips. Furthermore, the chips must bear a high price to cover the costs of manufacturing, as well as the return on initial capital and investment.
In U.S. Pat. No. 5,955,776, assigned to the same assignee as the present application and hereby incorporate by reference, a method and apparatus for manufacturing spherical-shaped semiconductor integrated circuits is disclosed. The present invention is specific to an apparatus and method for performing metal deposition on the circuits.
SUMMARY OF THE INVENTION
The present invention, accordingly, provides an apparatus and method for performing material (e.g. metal) deposition on semiconductor devices. In one embodiment, the apparatus provides an enclosure for defining a chamber. The chamber includes a metallic portion such as a conductor coil powered by a voltage generator. A gas, having a suspension of particles for treating the semiconductor devices, is introduced into the chamber and the powered conductor coil converts the as to inductively coupled plasma and vaporizes the particles. The particles can then be deposited on the semiconductor devices.
Several advantages result from the foregoing. For one, the semiconductor devices can be continuously introduced into the chamber to reduce or eliminate the need for a clean room environment. Also, the chamber can be maintained at a relatively high temperature above conventional semiconductor material warping or melting points. Further, the method of the present invention can be carried out in a relatively small space and eliminates the requirements for assembly and packaging facilities.
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Wang, Ma, Golz, Halpern & Schmitt/High-Quality MNS Capacitors Prepared By Jet Vapor Deposition At Room Temperature/pp. 12-14.
Heberlein & Pfender/Thermal Plasma Chemical Vapor Deposition/ pp. 1-7, 1-15.
Kong & Pfender/Synthesis Of Ceramic Powders In A Thermal DC Plasma Jet By Injection Of Liquid Precursors/ pp. 2-8.
Akira Ishikawa/Spherical Shaped Semiconductor Integrated Circuit/U.S. Serial No. 08/858,004/Filed: May 16, 1997; Abstract and 15 sheets of drawings.
Murzin Ivan Herman
Ramamurthi Ram K.
Ball Semiconductor Inc.
Bowers Charles
Haynes and Boone LLP
Kielin Erik J
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