Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-10-10
2004-12-14
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S329000, C438S667000, C257S277000, C257S531000
Reexamination Certificate
active
06830970
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing in a monolithic circuit a through via and an inductance. More specifically, it relates to an inductance of the type described in unpublished French patent application no. 01/13055 filed by the applicant on Oct. 10, 2001, which is incorporated herein by reference.
2. Discussion of the Related Art
The applicant has described in unpublished French patent application n
o
01/15307 filed on Nov. 27, 2001, which is incorporated herein by reference, a two-faced monolithic circuit associating active and passive components. Through vias enable establishing connections between the front surface and the rear surface.
FIGS. 1A and 1B
show a cross-section view and a top view of the inductance of French patent application n
o
01/13055. Inductance
10
is formed from a trench etched in a substrate
11
. The trench is conventionally obtained by anisotropic etching (for example, a plasma etching) which exposes a portion of substrate
11
according to a pattern of the type of that in FIG.
1
B. The trench is insulated from substrate
11
by a conformal insulating layer
12
, for example, a silicon oxide layer. The trench is then filled with a conductive material
15
forming inductance
10
. The inductance has the shape of a spiral (circular or not) exhibiting first and second ends
16
and
17
, first end
16
being substantially located at the center of the spiral.
When an inductance of the above type desired to a formed in a monolithic circuit comprised of one or several vias (not shown) crossing silicon substrate
11
to transfer contacts from one surface to the other, the number of manufacturing steps must be increased. Indeed, the size differences between the etchings necessary to the forming of inductance
10
and of vias (not shown) make it impossible to perform these etchings at the same time. Further, with usual etching processes using an etch mask, it is necessary to complete one of the two structures (inductance or via) before being able to etch the other structure. The holes or trenches formed must indeed be filled up to redeposit an etch mask of definition of the other structure.
The fact of having to form the two structures separately results in that only a single one of them can benefit from the advantages of having its conductive material insulated from the substrate by a thermal oxide formed at high temperature (on the order of 1000° C.). Indeed, if a second anneal step was carried out while one of the structures is completed, the high temperatures necessary would deteriorate this first structure.
SUMMARY OF THE INVENTION
The present invention aims at the forming of at least one inductance and of at least one through via in a monolithic circuit with common formation steps.
The present invention particularly aims at making the step of forming an insulating layer on the respective walls of the inductance trench and of the through holes of the vias common.
The present invention also aims at enabling formation of this insulating layer for coating the trenches and the vias with a same thermal oxide.
The present invention also aims at providing an inductance and via forming method in a monolithic circuit, which reduces or minimizes the number of manufacturing steps.
To achieve these and other objects, the present invention provides a method for manufacturing, in a monolithic circuit comprising a substrate, an inductance and a through via, in which is formed, from a first surface of the substrate, at least one trench according to the contour of the inductance to be formed; including the steps of forming, by laser in the substrate, a through hole at the location desired for the via; simultaneously insulating the surface of the trench and the hole; and depositing a conductive material in the trench and at least on the hole walls.
According to an embodiment of the present invention, the insulation is performed by thermal oxidation.
According to an embodiment of the present invention, the trench is formed by plasma etching.
According to an embodiment of the present invention, the step of deposition of a conductive material in the trench and on the walls of the holes is followed with a step of filling up the hole with an insulating material.
According to an embodiment of the present invention, the method further comprises a step of planarization of both surfaces of the substrate.
According to an embodiment of the present invention, a via is provided above a central end of the trench of the inductance.
The foregoing objects, features, and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
REFERENCES:
patent: 5363080 (1994-11-01), Breen
patent: 5398400 (1995-03-01), Breen
patent: 5545916 (1996-08-01), Koullias
patent: 5710068 (1998-01-01), Hill
patent: 5811868 (1998-09-01), Bertin et al.
patent: 6028348 (2000-02-01), Hill
patent: 6114937 (2000-09-01), Burghartz et al.
patent: 6236103 (2001-05-01), Bernstein et al.
patent: 6274937 (2001-08-01), Ahn et al.
patent: 6429096 (2002-08-01), Yanagida
patent: 6429764 (2002-08-01), Karam et al.
patent: 6504227 (2003-01-01), Matsuo et al.
patent: 2001/0017395 (2001-08-01), Takamura
patent: 2001/0023111 (2001-09-01), Yuan
patent: 0 932 204 (1999-07-01), None
patent: 1 054 417 (2000-11-01), None
French Preliminary Search Report from French Priority Application No. 01/15307, filed Nov. 27, 2001.
French Preliminary Search Report from French Priority Application No. 01/13055, filed Oct. 10, 2001.
French Preliminary Search Report from French Priority Application No. 02/07383, filed Jun. 14, 2002.
Patent Abstracts of Japan, vol. 014, No. 244 (E-0932) May 24, 1990 & JP 02 0677520, Mar. 7, 1990.
Patent Abstracts of Japan, vol. 018, No. 280 (E-1555) May 27, 1994 & JP 06 053414, Feb. 25, 1994.
Patent Abstracts of Japan, vol. 015, No. 187 (E-1062) May 14, 1991 & JP 03 048430, Mar. 1, 1991.
Patent Abstracts of Japan, vol. 013, No. 051 (E-712) Feb. 6, 1991 & JP 63 244761 Oct. 12, 1998.
Patent Abstracts of Japan, vol. 1999, No. 02, Feb. 26, 1999 & JP 10 303037, Nov. 13, 1998.
Method for Inductive Coil Fabrication, Kenneth Mason Publications, Hampshire, GB, No. 440, Dec. 2000, p. 2226 XP001052540.
Jorgenson Lisa K.
Lee Calvin
McClellan William R.
STMicroelectronics S.A.
Wolf Greenfield & Sacks P.C.
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