Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-17
2002-04-16
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S522000
Reexamination Certificate
active
06372582
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of forming indium-doped channel regions in a semiconductor substrate, whereby a desired retrograde-shaped indium concentration distribution profile is obtained. The present invention has particular utility in the manufacture of MOS-type transistor devices and semiconductor integrated circuits with improved processing methodology resulting in increased device reliability and performance characteristics. The present invention is also useful in the manufacture of CMOS devices and has particular applicability in fabricating high-density integration semiconductor devices with design features below about 0.18 &mgr;m, e.g., about 0.15 &mgr;m.
BACKGROUND OF THE INVENTION
The escalating requirements for high density and performance associated with ultra-large scale integration (ULSI) semiconductor devices, such as are currently manufactured or contemplated, require design features of 0.18 &mgr;m and below, such as 0.15 &mgr;m and below, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for economic competitiveness. The reduction of design features to 0.18 &mgr;m and below challenges the limitations of conventional semiconductor manufacturing techniques.
As feature sizes of MOS and CMOS devices have decreased to the sub-micron range, so-called “short-channel” effects have arisen which tend to limit device performance. For n-channel MOS transistors, the major limitation encountered is caused by hot-electron-induced instabilities. This problem occurs due to high electrical fields between the source and the drain, particularly near the drain, such that charge carriers, either electrons or holes, are injected into the gate or semiconductor substrate. Injection of hot carriers into the gate can cause gate oxide charging and threshold voltage instabilities which accumulate over time and greatly degrade device performance. In order to counter and thus reduce such instabilities, shallow junction, lightly- or moderately-doped source/drain extension type transistor structures have been developed.
For p-channel transistors, the major “short-channel” effect which limits device performance arises from “punch-through” effects which occur with relatively deep junctions. In such instances, there is a wider sub-surface depletion effect and it is easier for the field lines to go from the drain to the source, resulting in the above-mentioned “punch-through” current problems and device shorting. To minimize this effect, relatively shallow junctions are employed in forming p-channel MOS-type transistors.
The most satisfactory solution to date of hot carrier instability problems of MOS and CMOS-type sub-micron-dimensioned devices is the provision of lightly- or moderately-doped source/drain extensions driven just under the gate region, while the heavily-doped source/drain regions are laterally displaced away from the gate by the use of a pair of spacers on opposite sidewalls of the gate. Such structures are particularly advantageous because they do not have problems with large lateral diffusion and the channel length can be set precisely.
In operation of such devices, an input voltage is applied to the gate electrode and an output voltage is developed across the source and drain terminals. When the input voltage is applied to the gate electrode, a transverse electrical field is set up in the channel region between the source and drain regions. Variation of the transverse electrical field makes it possible to vary the conductance of the channel region, whereby an electric field controls the flow of current through the channel region between the source and drain regions. The channel region typically is lightly doped with an impurity of conductivity type opposite that of the source/drain regions, and the dopant impurity concentration distribution profile is typically uniform in the direction extending downwardly from the substrate surface. Such type MOS structures, however, are susceptible to “latch up”, wherein a very low resistance path is established between the V
SS
and V
DD
power lines, resulting in excessive current flow across the power supply terminals. Susceptibility to “latch-up” arises from the presence of complementary parasitic bipolar transistor structures, and is particular problematic with CMOS devices because such bipolar structires can electrically interact, in the manner of a pnpn diode. In the absence of triggering currents, such diodes act as reverse-biased junctions and do not conduct. However, it is possible for triggering currents to be established in a variety of ways during abnormal circuit operating conditions. Since many such parasitic pnpn structures can be present within a single chip, it is possible to trigger any one of them into a “latch up” condition and thus cause cessation of proper device functioning or even destroy the device due to locally high power dissipation.
One approach for control or elimination of “latch up” is the provision of retrograde doping profiles, i.e., a dopant impurity concentration distribution profile exhibiting a concentration peak deep below the substrate surface. Retrograde Channel Profiles (“RCP”) are employed in MOS and CMOS technology to reduce threshold voltage (V
T
) roll-off, i.e., sudden decrease of V
T
at very small (“sub-nominal”) device lengths. However, for RCP to be effective, the profile itself should meet certain criteria. First, the peak concentration should be located at an optimal depth from the surface because, on the one hand, if the impurity concentration peak is formed too close to the substrate surface, V
T
must be increased, while on the other hand, if the impurity concentration peak is too far below the substrate surface, the tendency for “latch up” will not be reduced or eliminated. Second, the profile along a vertical cut should be rather sharp, e.g., a delta function.
The use of boron doping (i.e., p-type doping) techniques for forming such RCP structures in the case of n-channel MOS and CMOS devices is problematic, principally due to the ease with which boron atoms diffuse in silicon semiconductor substrates. The rapidity of boron dopant atom diffusion upon thermal treatment for post-implantation activation/lattice damage relaxation disadvantageously results in a relatively flat or broadly-peaked concentration distribution profile rather than the desired sharply peaked profile.
The use of indium as an alternative p-type dopant to boron for RCP formation incurs a drawback in that indium easily diffuses into silicon oxide (e.g., SiO
2
) gate insulator layers, resulting in degradation of the gate oxide reliability. RCP formation with satisfactorily sharply-peaked profiles utilizing indium as a p-type dopant for channel regions of silicon-based MOS and CMOS transistor devices can be effected by implanting indium-containing ions In+ into a portion of the surface
2
of a silicon substrate
1
where a channel region is to be later formed at dosages and energies typically in the ranges of 1×10
12
−8×10
13
ions/cm
2
and 80-140 KeV, respectively, as illustrated by curve
3
of FIG.
1
(A). As is evident from the figure, indium implantation under such conditions results in a retrograde-shaped doping concentration profile extending to a depth d
1
below substrate surface
2
, with a maximum (or peak) indium concentration c
max
at a depth d
max
. However, as is apparent from FIG.
1
(B), which illustrates the state after thin gate insulator layer
6
formation on surface
2
, indium atoms and/or ions
4
remaining on the substrate surface and/or implanted in the uppermost stratum
5
of the substrate, rapidly diffuse into and degrade the reliability and insulative properties of the thin gate insulator layer
6
when the latter is of a silicon oxide thermally grown or otherwise formed on the substrate surface
2
, or when the latter is subjected to subsequent device formation processing at elevated temperatures conducive to dopant diffusion. Residual, post-implantation indium present on the sub
Hao Ming Yin
Ibok Effiong
Ishida Emi
Rouse Richard P.
Bowers Charles
Vesperman William C.
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