Independently accessed double-gate and tri-gate transistors...

Details Independently accessed double-gate and tri-gate transistors... Independently accessed double-gate and tri-gate transistors...

2004-09-29

2008-09-09

Huynh, Andy (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S157000, C438S164000, C257SE21442

Reexamination Certificate

active

07422946

ABSTRACT:
A method for forming first and second devices from first and second silicon bodies is described. A sacrificial layer allows gate regions to be defined with underlying insulating members. After the sacrificial layer and bodies are surrounded in a dielectric layer, the insulative member is removed from one of the bodies. After removal of the sacrificial layer, gate structures are formed. For one device, the gate surrounds three sides of the body, and for the other device two independent gates on the sides of the body result.

REFERENCES:
patent: 5346839 (1994-09-01), Sundaresan
patent: 5563077 (1996-10-01), Ha
patent: 5578513 (1996-11-01), Maegawa
patent: 6413802 (2002-07-01), Hu et al.
patent: 6475869 (2002-11-01), Yu
patent: 6483156 (2002-11-01), Adkisson et al.
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6562665 (2003-05-01), Yu
patent: 6680240 (2004-01-01), Maszara
patent: 6716684 (2004-04-01), Krivokapic et al.
patent: 6730964 (2004-05-01), Horiuchi
patent: 6764884 (2004-07-01), Yu et al.
patent: 6858478 (2005-02-01), Chau et al.
patent: 2002/0081794 (2002-06-01), Ito
patent: 2002/0167007 (2002-11-01), Yamazaki et al.
patent: 2003/0122186 (2003-07-01), Sekigawa et al.
patent: 2003/0151077 (2003-08-01), Mathew et al.
patent: 2004/0036118 (2004-02-01), Abadeer et al.
patent: 2004/0092062 (2004-05-01), Ahmed et al.
patent: 2004/0092067 (2004-05-01), Hanafi et al.
patent: 2004/0110097 (2004-06-01), Ahmed et al.
patent: 2004/0126975 (2004-07-01), Ahmed et al.
patent: 2004/0180491 (2004-09-01), Arai et al.
patent: 0 623 963 (1994-11-01), None
patent: WO 02/43151 (2002-05-01), None
patent: WO 2004/059726 (2004-07-01), None
V. Subramanian et al., “A Bulk-Si-Compatible Ultrathin-body SOI Technology for Sub-100m MOSFETS” Proceeding of the 57th Annual Device Research Conference, pp. 28-29 (1999).
Hisamoto et al., “A Folded-channel MOSFET for Deepsub-tenth Micron Era”, 1998 IEEE International Electron Device Meeting Technical Digest, pp. 1032-1034 (1998).
Huang et al., “Sub 50-nm FinFET: PMOS”, 1999 IEEE International Electron Device Meeting Technical Digest, pp. 67-70 (1999).
Auth et al., “Vertical, Fully-Depleted, Surroundings Gate MOSFETS On sub-0.1um Thick Silicon Pillars”, 1996 54th Annual Device Research Conference Digest, pp. 108-109 (1996).
Hisamoto et al., “A Fully Depleted Lean-Channel Transistor (DELTA)-A Novel Vertical Ultrathin SOI MOSFET”, IEEE Electron Device Letters, V. 11(1), pp. 36-38 (1990).
Jong-Tae Park et al., “Pi-Gate SOI MOSFET” IEEE Electron Device Letters, vol. 22, No. 8, Aug. 2001, pp. 405-406.
Hisamoto, Digh et al. “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm”, IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
International Search Report PCT/US 03/26242.
International Search Report PCT/US 03/39727.
International Search Report PCT/US 03/40320.
Int'l Search Report for PCT/US2005/035380, mailing date Feb. 13, 2006, 4 pages.
Fried, David M. et al,High-Performance P-Type Independent-Gate FinFETs, IEEE Electron Device Letters, vol. 25, No. 4, Apr. 2004, pp. 199-201.
Fried, David M. et al,Improved Independent Gate N-Type FinFET Fabrication and Characterization, IEEE Electron Device Letters, vol. 24, No. 9, Sep. 2003, pp. 592-594.
Kuo, Charles et al,A Capacitorless Double Gate DRAM Technology for Sub-100-nm Embedded and Stand-Alone Memory Application, IEEE Trans for Electron Dev, vol. 50, No. 12, Dec. 2003, pp. 2408-2416.
Kuo, Charles et al,A Capacitorless Double-Gate DRAM Cell Design for High Density Applications, 2002 IEEE Int'l Electron Devices Meeting Technical Digest, Dec. 2002, pp. 843-846.
Ohsawa, Takashi et al,Memory Design Using a One-Transistor Gain Cell on SOI, IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1510-1522.
Tanaka, T. et al,Scalability Study on a Capacitorless IT-DRAM: From Single-gate PD-SOI to Double-gate FinDRAM, 2004 IEEE Int'l Electron Devices Meeting Techical Digest, Dec. 2004, 4 pages.

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