Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-05-02
2006-05-02
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S290000, C438S303000
Reexamination Certificate
active
07037790
ABSTRACT:
A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member portions are removed from above the semiconductor body of the tri-gate device but not the I-gate device. This facilitates the formation of metallization on three sides of the tri-gate device, and the formation of independent gates for the I-gate device.
REFERENCES:
patent: 5346839 (1994-09-01), Sundaresan
patent: 5563077 (1996-10-01), Ha
patent: 5578513 (1996-11-01), Maegawa
patent: 5658806 (1997-08-01), Lin et al.
patent: 5716879 (1998-02-01), Choi et al.
patent: 6159808 (2000-12-01), Chuang
patent: 6376317 (2002-04-01), Forbes et al.
patent: 6413802 (2002-07-01), Hu et al.
patent: 6475869 (2002-11-01), Yu
patent: 6483156 (2002-11-01), Adkisson et al.
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6562665 (2003-05-01), Yu
patent: 6611029 (2003-08-01), Ahmed et al.
patent: 6680240 (2004-01-01), Maszara
patent: 6716684 (2004-04-01), Krivokapic et al.
patent: 6730964 (2004-05-01), Horiuchi
patent: 2002/0081794 (2002-06-01), Ito
patent: 2002/0167007 (2002-11-01), Yamazaki et al.
patent: 0 623 963 (1994-11-01), None
patent: WO 02/43151 (2002-05-01), None
U.S. Appl. No. 10/816,282, filed Mar. 31, 2004, Chang.
European Patent Office, International Search Report for International Application No. PCT/US 03/39727, Apr. 27, 2004, 6 pages.
European Patent Office, International Search Report for International Application No. PCT/US 03/26242, Jan. 26, 2004, 8 pages.
European Patent Office, International Search Report for International Application No. PCT/US 03/40320, Jun. 2, 2004, 6 pages.
Subramanian, V. et al.,A Bulk-Si-Compatible Ultrathin-body SOI Technology for Sub-100nm MOSFETS,Proceedings of the 57th Annual Device Research Conference, Jun. 1999, pp. 28-29.
Hisamoto, Digh et al.,A Folded-channel MOSFET for Deep-sub-tenth Micron Era,1998 IEEE International Electron Devices Meeting Technical Digest, Dec. 1998, pp. 1032-1034.
Huang, Xuejue et al.,Sub 50-nm FinFet: PMOS,1999 IEEE International Electron Devices Meeting Technical Digest, Dec. 1999, pp. 67-70.
Auth, C. et al.,Vertical Fully-Depleted, Surrounding Gate MOSFETS On sub-0.1um Thick Silicon Pillars, 54th Annual Device Research Conference Digest, Jun. 1996, pp. 108-109.
Hisamoto et al.,A Fully Depleted Lean-Channel Transistor(DELTA)—A Novel Vertical Ultrathin SOI MOSFET, IEEE Electron Device Letters, vol. 11, No. 1, Jan. 1990, pp. 36-38.
Park, Jong-Tae et al.,Pi-Gate SOI MOSFET, IEEE Electron Device Letters, vol. 22, No. 8, Aug. 2001, pp. 405-406.
Hisamoto, Digh et al.,FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm, IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Fried, David M. et al.,High-Performance P-Type Independent-Gate FinFETs, IEEE Electron Device Letters, vol. 25, No. 4, Apr. 2004, pp. 199-201.
Fried, David M. et al.,Improved Independent Gate N-Type FinFET Fabrication and Characterization, IEEE Electron Device Letters, vol. 24, No. 9, Sep. 2003, pp. 592-594.
Kuo, Charles et al.,A Capacitorless Double Gate DRAM Technology for Sub-100-nm Embedded and Stand-Alone Memory Applications, IEEE Transactions on Electron Devices, vol. 50, No. 12, Dec. 2003, pp. 2408-2416.
Kuo, Charles et al.,A Capacitorless Double-Gate DRAM Cell Design for High Density Applications, 2000 IEEE International Electron Devices Meeting Technical Digest, Dec. 2002, pp. 843-846.
Ohsawa, Takashi et al.,Memory Design Using a One-Transistor Gain Cell on SOI, IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1510-1522.
Tanaka, T. et al.,Scalability Study on a Capacitorless 1T-DRAM: From Single-gate PD-SOI to Double-gate FinDRAM, 2004 IEEE International Electron Devices Meeting Technical Digest, Dec. 2004, 4 pages.
Chang Peter L. D.
Doyle Brian S.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Tsai H. Jey
LandOfFree
Independently accessed double-gate and tri-gate transistors... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Independently accessed double-gate and tri-gate transistors..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Independently accessed double-gate and tri-gate transistors... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3618335