Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2007-08-23
2008-08-12
Nguyen, Tan T. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Testing
C365S189070, C365S200000, C365S230030
Reexamination Certificate
active
07411848
ABSTRACT:
A method of testing, polling and trimming memory pages in different memory banks simultaneously is presented, using a cache memory located in each one of the memory banks. The cache memory is at least as large as the individual memory pages and is used to record the programming voltage required to obtain the specified programming speed as well as the location of defective memory elements. A local on chip state machine may be used to accelerate the programming rate, and there may be a state machine per memory bank. With such an arrangement, the amount of testing time at wafer probe and final packaged device test may be reduced up to 40%, depending upon the number of memory pages tested in parallel.
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“U.S. Appl. No. 11/382,658, Notice of Allowance mailed Jun. 26, 2007.”, 8 pgs.
Gatzemeier Scott N.
Lee June
Micro)n Technology, Inc.
Nguyen Tan T.
Schwegman Lundberg & Woessner, P.A.
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