Independent-gate controlled asymmetrical memory cell and...

Details Independent-gate controlled asymmetrical memory cell and... Independent-gate controlled asymmetrical memory cell and...

2006-02-27

2008-08-26

Yoha, Connie C (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S226000

Reexamination Certificate

active

07417889

ABSTRACT:
Techniques are provided for employing independent gate control in asymmetrical memory cells. A memory circuit, such as an SRAM circuit, can include a number of bit line structures, a number of word line structures that intersect the bit line structures to form a number of cell locations, and a number of asymmetrical memory cells located at the cell locations. Each of the asymmetrical cells can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each of the cells can include a number of field effect transistors (FETS), and at least one of the FETS can be configured with separately biased front and back gates. One gate can be biased separately from the other gate in a predetermined manner to enhance read stability of the asymmetrical cell.

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