Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Patent
1997-02-21
1999-06-08
Niebling, John F.
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
438405, 438400, H01L 2176
Patent
active
059100176
ABSTRACT:
A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after etch back. In a silicon-on-insulator (SOI) device, dummy active areas are inserted between the active areas in order to maintain the thickness of the refill layer between the mesas to insure proper isolation between the active devices. The technique is also applicable to non-SOI devices.
REFERENCES:
patent: 5234861 (1993-08-01), Roisen et al.
patent: 5264387 (1993-11-01), Beyer et al.
Donaldson Richard L.
Hoel Carlton H.
Jones Josetta I.
Niebling John F.
Texas Instruments Incorporated
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