Increasing capacitance for high density DRAM by microlithography

Details Increasing capacitance for high density DRAM by microlithography Increasing capacitance for high density DRAM by microlithography

1998-03-05

2000-02-01

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, H01L 218242

Patent

active

060202343

ABSTRACT:
A method is disclosed for increasing the capacitance of high-density DRAM devices by microlithographic patterning. A semiconductor substrate having a MOS transistor comprising a gate and source/drain regions, and a word line and a bit line is provided. A layer of inter-poly oxide is deposited over the substrate and planarized. Contact holes are etched in the oxide layer until the substrate is exposed. A layer of photoresist is next blanket deposited over the substrate. Using microlithographic methods, the photoresist is then patterned with in-line or staggered micron size features and the underlying inter-poly oxide layer is etched using the photoresist as a mask. The resulting inter-poly oxide surface, therefore, acquires the shape of a micro-folded topography having a roughened surface area of many folds larger than the original flat surface. A first conductive layer such as polysilicon is conformally deposited over the microlithoqraphically roughened surface forming the storage electrode of the capacitor which is completed by forming a high dielectric oxide such as ONO over the first polysilicon and then depositing a second polysilicon to form the upper electrode of the capacitor.

REFERENCES:
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patent: 5604148 (1997-02-01), Lur
patent: 5744390 (1998-04-01), Chao
patent: 5763304 (1998-06-01), Tseng
patent: 5879985 (1999-03-01), Gambino et al.

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