Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-10-18
1998-01-20
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438637, H01L 218242
Patent
active
057100748
ABSTRACT:
A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a lower, or storage node electrode, for the STC structure, consisting of multiple, polysilicon mesa structures, as well as polysilicon spacers, on the sides of the polysilicon mesas, with the polysilicon spacers protruding above the top surface of the polysilicon mesas. This is accomplished by initially creating a composite mesa structure, of an insulator layer, on a partially etched polysilicon layer. After creation of the polysilicon spacer, on the sides of the composite, mesa structure, the insulator is selectively removed, resulting in polysilicon mesas, with protruding polysilicon spacers. This storage node configuration results in an significant increase of surface area, when compared to storage nodes fabricated with flat topographies.
REFERENCES:
patent: 5061650 (1991-10-01), Dennison et al.
patent: 5447882 (1995-09-01), Kim
patent: 5468670 (1995-11-01), Ryou
patent: 5492850 (1996-02-01), Ryou
Ackerman Stephen B.
Chaudhari Chandra
Saile George O.
Vanguard International Semiconductor Corporation
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