Increased surface area capacitor via use of a novel reactive ion

Details Increased surface area capacitor via use of a novel reactive ion Increased surface area capacitor via use of a novel reactive ion

1997-03-10

1998-06-02

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438255, H01L 218242

Patent

active

057598916

ABSTRACT:
A method of creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a saw-toothed topography for the top surface of a polysilicon storage node electrode. The saw-toothed topography is obtained by placing intrinsic HSG polysilicon spots on an underlying doped polysilicon layer. An anisotropic RIE procedure, using SF.sub.6, as an etchant, removes doped polysilicon at a faster rate then the removal rate of the masking intrinsic HSG polysilicon spots, resulting in a saw-toothed topography in the polysilicon storage node electrode, comprised of raised features of HSG polysilicon spots, on unetched doped polysilicon, and lower features of etched, doped polysilicon. The saw-toothed topography, increases the surface area of the polysilicon storage node electrode, thus furnishing capacitance increases.

REFERENCES:
patent: 5254503 (1993-10-01), Kenney
patent: 5427974 (1995-06-01), Lur et al.
patent: 5464791 (1995-11-01), Hirota
patent: 5492848 (1996-02-01), Lur et al.
patent: 5512768 (1996-04-01), Lur et al.
Watanabe et al, "Hemispherical Grain Silicon for High Density DRAMs", Solid State Technology, Jul., 1992, pp. 29-33.

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